INTEGRATED CIRCUITS 80C51/87C51/80C52/87C52 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.7 V5.5 V), low power, high speed (33 MHz), 128/256 B RAM Product specification 2000 Aug 07 Replaces datasheet 80C51/87C51/80C31 of 2000 Jan 20 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C51/87C51/80C52/87C52 4 K/8 K OTP/ROM low voltage (2.7 V5.5 V), low power, high speed (33 MHz), 128/256 B RAM DESCRIPTION FEATURES The Philips 80C51/87C51/80C52/87C52 is a high-performance 8051 Central Processing Unit static 80C51 design fabricated with Philips high-density CMOS 4k 8 ROM (80C51) technology with operation from 2.7 V to 5.5 V. 8k 8 ROM (80C52) The 8xC51 and 8xC52 contain a 128 8 RAM and 256 8 RAM 128 8 RAM (80C51) respectively, 32 I/O lines, three 16-bit counter/timers, a six-source, 256 8 RAM (80C52) four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex Three 16-bit counter/timers UART, and on-chip oscillator and clock circuits. Boolean processor In addition, the device is a low power static design which offers a Full static operation wide range of operating frequencies down to zero. Two software Low voltage (2.7 V to 5.5 V 16 MHz) operation selectable modes of power reductionidle mode and power-down Memory addressing capability mode are available. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue 64k ROM and 64k RAM functioning. The power-down mode saves the RAM contents but Power control modes: freezes the oscillator, causing all other chip functions to be Clock can be stopped and resumed inoperative. Since the design is static, the clock can be stopped without loss of user data and then the execution resumed from the Idle mode point the clock was stopped. Power-down mode CMOS and TTL compatible SELECTION TABLE For applications requiring more ROM and RAM, see the 8XC54/58 TWO speed ranges at V = 5 V CC and 8XC51RA+/RB+/RC+/80C51RA+ data sheet. 0 to 16 MHz 0 to 33 MHz Note: 80C31/80C32 is specified in separate data sheet. Three package styles ROM/EPROM RAM Size Programmable Hardware Extended temperature ranges Memory Size (X by 8) Timer Counter Watch Dog (X by 8) (PCA) Timer Dual Data Pointers 80C31*/80C51/87C51 Security bits: ROM (2 bits) 0K/4K 128 No No OTP/EPROM (3 bits) 80C32*/80C52/87C52 Encryption array 64 bytes 0K/8K/16K/32K 256 No No 4 level priority interrupt 80C51RA+/8XC51RA+/RB+/RC+ 6 interrupt sources 0K/8K/16K/32K 512 Yes Yes Four 8-bit I/O ports 8XC51RD+ Fullduplex enhanced UART 64K 1024 Yes Yes Framing error detection Automatic address recognition Programmable clock out Asynchronous port reset Low EMI (inhibit ALE and slew rate controlled outputs) Wake-up from Power Down by an external interrupt 2 2000 Aug 07 8530169 24291