PCA9537DP,118 NXP

PCA9537 2 4-bit I C-bus and SMBus low power I/O port with interrupt and reset Rev. 7 8 September 2021 Product data sheet COMPANY PUBLIC 1 General description The PCA9537 is a 10-pin CMOS device that provides 4 bits of General Purpose parallel 2 Input/Output (GPIO) expansion with interrupt and reset for I C-bus/SMBus applications. 2 It was developed to enhance the NXP Semiconductors family of I C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push-buttons, LEDs, fans, etc. The PCA9537 consists of a 4-bit Configuration register (input or output selection), 4-bit Input Port register, 4-bit Output Port register and a 4-bit Polarity Inversion register (active HIGH or active LOW operation). The system controller can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system controller. The PCA9537 open-drain interrupt output (INT) is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system controller that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. The RESET pin causes the same reset/initialization to occur without de-powering the device. 2 2 The I C-bus address is fixed and allows only one device on the same I C-bus/SMBus. 2 Features and benefits 2 4-bit I C-bus GPIO with interrupt and reset Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant I/Os Polarity Inversion register Active LOW interrupt output Active LOW reset input Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 4 I/O pins that default to 4 inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Offered in TSSOP10 packageNXP Semiconductors PCA9537 2 4-bit I C-bus and SMBus low power I/O port with interrupt and reset 3 Ordering information Table 1.Ordering information T = -40 C to +85 C amb Type number Topside Package mark Name Description Version PCA9537DP 9537 TSSOP10 plastic thin shrink small outline package 10 SOT552-1 leads body width 3 mm 3.1 Ordering options Table 2.Ordering options Type number Orderable part Package Packing method Minimum Temperature number order quantity 1 PCA9537DP PCA9537DP,118 TSSOP10 REEL 13 Q1/T1 2500 T = -40 C to +85 C amb *STANDARD MARK SMD PCA9537DPZ TSSOP10 REEL 13 Q1/T1 2500 T = -40 C to +85 C amb *STANDARD MARK 2 SSB 1 Discontinued in 202104010DN - drop in replacement is PCA9537DPZ - this is documented in PCN 2020104008A. 2 This packing method uses a Static Shielding Bag (SSB) solution. Material should be kept in the sealed bag between uses. 4 Block diagram PCA9537 IO0 SCL INPUT IO1 SDA FILTER 4-bit IO2 INPUT/ 2 IO3 I C-BUS/SMBus OUTPUT CONTROL PORTS write pulse V DD POWER-ON read pulse RESET RESET V DD V SS INT LP FILTER 002aae634 Remark: All I/Os are set to inputs at reset. Figure 1.Block diagram of PCA9537 PCA9537 All information provided in this document is subject to legal disclaimers. NXP B.V. 2021. All rights reserved. Product data sheet Rev. 7 8 September 2021 COMPANY PUBLIC 2 / 25