PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL
clock driver
Rev. 05 9 October 2008 Product data sheet
1. General description
The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high
performance clock tree designs. With output frequencies of up to 125 MHz, and output
skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The
devices employ a fully differential PLL design to minimize cycle-to-cycle and phase jitter.
The PCK953 has a differential LVPECL reference input, along with an external feedback
input. These features make the PCK953 ideal for use as a zero delay, low skew fan-out
buffer. The device performance has been tuned and optimized for zero delay performance.
The MR/OE input pin will reset the internal counters and 3-state the output buffers when
driven HIGH.
The PCK953 is fully 3.3 V compatible and requires no external loop lter components. All
control inputs accept LVCMOS or LVTTL compatible levels, while the outputs provide
LVCMOS levels with the ability to drive terminated 50 transmission lines. For series
terminated 50 lines, each of the PCK953 outputs can drive two traces, giving the device
an effective fan-out of 1 : 18. The device is packaged in a 7 mm 7 mm 32-lead LQFP
package to provide the optimum combination of board density and performance.
2. Features
n Fully integrated PLL
n Output frequency up to 125 MHz in PLL mode
n Outputs disable in high-impedance
n LQFP32 packaging
n 55 ps cycle-to-cycle jitter typical
n 9 mA quiescent current typical
n 60 ps static phase offset typicalPCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
3. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
PCK953BD LQFP32 plastic low prole quad at package; 32 leads; body 7 7 1.4 mm SOT358-1
PCK953BD/G
Also refer to Table 8 Packing information.
4. Functional diagram
QFB
PECL_CLK
7
PECL_CLK
VCO Q0 to Q6
PHASE
LPF 200 MHz 4
DETECTOR
2
to 500 MHz
FB_CLK
Q7
VCO_SEL
BYPASS
MR/OE
PLL_EN
002aae138
Fig 1. Functional diagram
5. Pinning information
5.1 Pinning
1 24
V Q1
CCA
2 23
FB_CLK V
CCO
3 22
n.c. Q2
4 21
n.c. PCK953BD GNDO
PCK953BD/G
5 20
n.c. Q3
6 19
n.c. V
CCO
7 18
GNDI Q4
8 17
PECL_CLK GNDO
002aae137
Fig 2. Pin conguration for LQFP32
PCK953_5 NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 9 October 2008 2 of 15
PECL_CLK 9 32 VCO_SEL
MR/OE 10 31 BYPASS
V 11 30 PLL_EN
CCO
Q7 12 29 GNDO
GNDO 13 28 QFB
Q6 14 27 V
CCO
V 15 26 Q0
CCO
Q5 16 25 GNDO