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is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
February 2008
74LVX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop
Features General Description
Input voltage level translation from 5V to 3V The LVX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Ideal for low power/low noise 3.3V applications
Information at the input is transferred to the outputs on
Guaranteed simultaneous switching noise level and
the positive edge of the clock pulse. After the Clock
dynamic threshold performance
Pulse input threshold voltage has been passed, the Data
input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
LOW input to S (Set) sets Q to HIGH level
D
LOW input to C (Clear) sets Q to LOW level
D
Clear and Set are independent of clock
Simultaneous LOW on C and S makes both Q and
D D
HIGH
Q
Ordering Information
Order Package
Number Number Package Description
74LVX74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVX74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVX74 Rev. 1.4.0