74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs March 1998 Revised October 2004 74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16601 is an 18-bit universal bus transceiver which 1.4V to 3.6V V supply operation CC combines D-type latches and D-type flip-flops to allow data 3.6V tolerant inputs and outputs flow in transparent, latched, and clocked modes. t (A to B, B to A) PD Data flow in each direction is controlled by output-enable 2.9 ns max for 3.0V to 3.6V V (OEAB and OEBA), latch-enable (LEAB and LEBA), and CC clock (CLKAB and CLKBA) inputs. The clock can be con- Power-down high impedance inputs and outputs trolled by the clock-enable (CLKENAB and CLKENBA) Supports live insertion/withdrawal (Note 1) inputs. For A-to-B data flow, the device operates in the Static Drive (I /I ) OH OL transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-to- 24 mA 3.0V V CC LOW logic level. If LEAB is LOW, the A bus data is stored Uses proprietary noise/EMI reduction circuitry in the latch/flip-flop on the LOW-to-HIGH transition of Latchup performance exceeds 300 mA CLKAB. When OEAB is LOW, the outputs are active. When ESD performance: OEAB is HIGH, the outputs are in the high-impedance state. Human body model > 2000V Data flow for B to A is similar to that of A to B but uses Machine model >200V OEBA, LEBA, CLKBA and CLKENBA. Also packaged in plastic Fine-Pitch Ball Grid Array The VCX16601 is designed for low voltage (1.4V to 3.6V) (FBGA) (Preliminary) V applications with I/O capability up to 3.6V. CC Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V through a pull-up resistor the minimum CC The VCX16601 is fabricated with an advanced CMOS value of the resistor is determined by the current-sourcing capability of the technology to achieve high speed operation while maintain- driver. ing low CMOS power dissipation. Ordering Code: Order Number Package Number Package Description 74VCX16601GX BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 2) (Preliminary) TAPE and REEL 74VCX16601MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 3) Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. 2004 Fairchild Semiconductor Corporation DS500126 www.fairchildsemi.comConnection Diagrams Pin Descriptions Pin Assignment for TSSOP Pin Names Description OEAB, OEBA Output Enable Inputs (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, CLKBA Clock Inputs CLKENAB, CLKENBA Clock Enable Inputs A A Side A Inputs or 3-STATE Outputs 1 18 B B Side B Inputs or 3-STATE Outputs 1 18 FBGA Pin Assignments 12 3 4 56 A A A OEAB CLKENAB B B 2 1 1 2 B A A LEAB CLKAB B B 4 3 3 4 C A A V V B B 6 5 CC CC 5 6 D A A GND GND B B 8 7 7 8 E A A GND GND B B 10 9 9 10 F A A GND GND B B 12 11 11 12 G A A V V B B 14 13 CC CC 13 14 H A A OEBA CLKBA B B 16 15 15 16 J A A LEBA CLKENBA B B 17 18 18 17 Truth Table (Note 4) Inputs Outputs CLKENAB OEAB LEAB CLKAB A B n n XH X X X Z Pin Assignment for FBGA XL H X L L XL H X H H HL L X XB (Note 5) 0 HL L X XB (Note 5) 0 LL L LL LL L HH LL L L XB (Note 5) 0 LL L H XB (Note 6) 0 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance (Top Thru View) Note 4: A-to-B data flow is shown B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. Note 5: Output level before the indicated steady-state input conditions were established. Note 6: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. www.fairchildsemi.com 2 74VCX16601