CAT24C256 2 256 kb I C CMOS Serial EEPROM Description The CAT24C256 is a 256 kb Serial CMOS EEPROM, internally organized as 32,768 words of 8 bits each. CAT24C256 Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature 65 to +150 C Voltage on any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than 0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may CC undershoot to no less than 1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns. CC Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter Min Units N (Notes 3, 4) Endurance 1,000,000 Program/Erase Cycles END T Data Retention 100 Years DR 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 3. Page Mode, V = 5 V, 25C. CC 4. The new product revision (E) uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte has to be written, 4 bytes (including the ECC bits) are reprogrammed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles. Table 3. D.C. OPERATING CHARACTERISTICS Mature Product (Rev D) (V = 2.5 V to 5.5 V, T = 40C to +125C, and V = 1.8 V to 5.5 V, T = 40C to +85C, unless otherwise specied.) CC A CC A Symbol Parameter Test Conditions Min Max Units I Read Current Read, f = 400 kHz 1 mA CCR SCL I Write Current Write, f = 400 kHz 3 mA CC SCL I Standby Current All I/O Pins at GND or V T = 40C to +85C 1 A SB CC A T = 40C to +125C 2 A I I/O Pin Leakage Pin at GND or V T = 40C to +85C 1 A L CC A T = 40C to +125C 2 A V Input Low Voltage 0.5 V x 0.3 V IL CC V Input High Voltage V x 0.7 V + 0.5 V IH CC CC V Output Low Voltage V 2.5 V, I = 3.0 mA 0.4 V OL1 CC OL V Output Low Voltage V < 2.5 V, I = 1.0 mA 0.2 V OL2 CC OL Table 4. PIN IMPEDANCE CHARACTERISTICS Mature Product (Rev D) (V = 2.5 V to 5.5 V, T = 40C to +125C, and V = 1.8 V to 5.5 V, T = 40C to +85C, unless otherwise specied.) CC A CC A Symbol Parameter Conditions Max Units C (Note 5) SDA I/O Pin Capacitance V = 0 V 8 pF IN IN C (Note 5) Input Capacitance (other pins) V = 0 V 6 pF IN IN I (Note 6) WP Input Current V < V , V = 5.5 V 130 A WP IN IH CC V < V , V = 3.3 V 120 IN IH CC V < V , V = 1.8 V 80 IN IH CC V > V 1 IN IH 5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 6. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull down is relatively strong therefore the external driver must be able to supply the pulldown current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pulldown reverts to a weak current source. The CC variable WP input impedance is available only for Die Rev. C and higher.