Product Information

CAT25M02VI-GT3

CAT25M02VI-GT3 electronic component of ON Semiconductor

Datasheet
EEPROM 2MB SPI SER CMOS

Manufacturer: ON Semiconductor
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete
Availability Price Quantity
0 - WHS 1

MOQ : 3000
Multiples : 3000

Stock Image

CAT25M02VI-GT3
ON Semiconductor

3000 : USD 4.2412
N/A

Obsolete
0 - WHS 2

MOQ : 3000
Multiples : 3000

Stock Image

CAT25M02VI-GT3
ON Semiconductor

3000 : USD 4.5597
N/A

Obsolete
0 - WHS 3

MOQ : 1
Multiples : 1

Stock Image

CAT25M02VI-GT3
ON Semiconductor

1 : USD 7.2136
10 : USD 4.6907
100 : USD 4.2847
3000 : USD 4.0709
N/A

Obsolete
     
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Package / Case
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Supply Voltage - Max
Minimum Operating Temperature
Maximum Operating Temperature
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Access Time
Data Retention
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CAT25M02 EEPROM Serial 2-Mb SPI Description The CAT25M02 is a EEPROM Serial 2Mb SPI device internally organized as 256Kx8 bits. This features a 256byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required www.onsemi.com bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAT25M02 device. The device features software and hardware write protection, including partial as well as full array protection. OnChip ECC (Error Correction Code) makes the device suitable SOIC8 WLCSP8 V SUFFIX C8A SUFFIX for high reliability applications. CASE 751BD CASE 567NM Features 5 / 10 MHz SPI Compatible PIN CONFIGURATIONS Supply Voltage Range: 1.7 V to 5.5 V CS V CC 1 SPI Modes (0,0) & (1,1) SO HOLD 256byte Page Write Buffer WP SCK Additional Identification Page with Permanent Write Protection V SI SS SOIC (V) (Top View) Selftimed Write Cycle Hardware and Software Protection V CS CC Block Write Protection Protect 1/4, 1/2 or Entire EEPROM Array HOLD SO Low Power CMOS Technology 1,000,000 Program/Erase Cycles SCK WP SI V 100 Year Data Retention SS Industrial and Extended Temperature Range WLCSP (C8A) (Top View) 8lead SOIC and 8ball WLCSP Packages and Die Sales* These Devices are PbFree, Halogen Free/BFR Free and are RoHS PIN FUNCTION Compliant V Pin Name Function CC CS Chip Select SI SO Serial Data Output CS WP Write Protect CAT25M02 SO WP V Ground SS HOLD SI Serial Data Input SCK SCK Serial Clock HOLD Hold Transmission Input V SS V Power Supply CC Figure 1. Functional Symbol *Please contact factory for Die Sales Information ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: June, 2018 Rev. 3 CAT25M02/DCAT25M02 DEVICE MARKINGS 25M02A AYMZZZ 2MSA ALYW SOIC8 Package WLCSP8 Package 25M02A = Specific Device Code 2MSA = Specific Device Code A = Assembly Site A = Assembly Site Y = Year of Production, Last Number L = Wafer Lot Number M = Assembly Operation Month Y = Year of Production, Last Number ZZZ = Assembly Lot Number, Last Three Numbers W = Work Week Number Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Operating Temperature 40 to +125 C Storage Temperature 65 to +150 C Voltage on any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than 0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may CC undershoot to no less than 1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns. CC Table 2. RELIABILITY CHARACTERISTICS (Note 4) Symbol Parameter Min Units N (Notes 2, 3) Endurance 1,000,000 Program/Erase Cycles END T Data Retention 100 Years DR 2. Page Mode, V = 5 V, 25C. CC 3. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte has to be written, 4 bytes (including the ECC bits) are reprogrammed. It is recommended to write by multiple of 4 bytes located at addresses 4N, 4(N+1), 4(N+2), 4(N+3), in order to benefit from the maximum number of write cycles. 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. www.onsemi.com 2

Tariff Desc

8542.32.00 32 No ..CMOS and MOS Read Only Memory and Programmable Read Only Memory whether erasable or non-erasable (for example, flash memory, EPROM, E2PROM, EAPROM, NOVRAM, ROM and PROM)
Aptina / ON Semiconductor
FAIRCHILD
FAIRCHILD (ON SEMICONDUCTOR)
Fairchild Semiconductor
FS8
FSC
ON
ON SEMI
ON Semicon
ON SEMICONDUCTOR
ON SEMICONDUCTOR (FAIRCHILD)
ON Semiconductor / Fairchild
ON4
ON5
onsemi
ON-SEMI
onsemi / Fairchild
OOF
Xsens / Fairchild

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