CAT28LV256
256K-Bit CMOS PARALLEL EEPROM
FEATURES
CMOS and TTL Compatible I/O
3.0V to 3.6V Supply
Read Access Times: 200/250/300 ns Automatic Page Write Operation:
1 to 64 Bytes in 10ms
Low Power CMOS Dissipation:
Page Load Timer
Active: 15 mA Max.
Standby: 150 A Max. End of Write Detection:
Toggle Bit
Simple Write Operation:
DATADATADATADATADATA Polling
On-Chip Address and Data Latches
Hardware and Software Write Protection
Self-Timed Write Cycle with Auto-Clear
Fast Write Cycle Time: 100,000 Program/Erase Cycles
10ms Max.
100 Year Data Retention
Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28LV256 is a fast, low power, low voltage The CAT28LV256 is manufactured using Catalysts
2
CMOS Parallel E PROM organized as 32K x 8-bits. It advanced CMOS floating gate technology. It is designed
requires a simple interface for in-system programming. to endure 100,000 program/erase cycles and has a data
On-chip address and data latches, self-timed write cycle retention of 100 years. The device is available in JEDEC
with auto-clear and V power up/down write protection approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
CC
eliminate additional timing and protection hardware. packages.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28LV256 features hardware and software write
protection.
BLOCK DIAGRAM
32,768 x 8
ROW
ADDR. BUFFER
A A 2
E PROM
6 14
DECODER
& LATCHES
ARRAY
INADVERTENT HIGH VOLTAGE
64 BYTE PAGE
V WRITE GENERATOR
CC
REGISTER
PROTECTION
CE
CONTROL
OE
LOGIC
WE
I/O BUFFERS
DATA POLLING
AND
TIMER
TOGGLE BIT
I/O I/O
0 7
ADDR. BUFFER
A A
COLUMN
0 5
& LATCHES
DECODER
28LV256 F01
2009 SCILLC. All rights reserved. Doc. No. MD-1071, Rev. E
1
Characteristics subject to change without noticeCAT28LV256
PIN CONFIGURATION
PLCC Package (N, G)
DIP Package (P, L)
A 1 28 V
14 CC
A 2 27 WE
12
A 3 26 A
4321 323130
7 13
5 29
A A
A 4 25 A
6 8
6 8
6 28
A A
A 5 24 A
5 9
5 9
7 27
A A
A 6 23 A
4 11
4 11
8 26
A NC
A 7 22 OE
3
3
9 25
A TOP VIEW OE
A 8 21 A
2
2 10
10 24
A A
A 9 20 CE
1 10
1
11 23
A CE
A 10 19 I/O
0
0 7
12 22
NC I/O
I/O 11 18 I/O
7
0 6
13 21
I/O
I/O 12 17 I/O I/O
0
1 5 6
14 15 16 17 18 19 20
I/O 13 16 I/O
2 4
V 14 15 I/O
SS 3
TSOP Top View (8mm X 13.4mm) (H)
OE 28
1 A
10
A 2 27
CE
11
A 3 26
I/O
9
7
A 4 25 I/O
8 6
A
5 24 I/O
13
5
WE 6 23 I/O
4
V
7 22 I/O
CC
3
A 8 21 GND
14
A 9 20 I/O
12 2
A 10 19
I/O
7
1
A 11 18
I/O
6 0
A 12 17 A
5 0
A 13 16
A
4 1
A 14 15
A
3 2
PIN FUNCTIONS
Pin Name Function Pin Name Function
A A Address Inputs WE Write Enable
0 14
I/O I/O Data Inputs/Outputs V 3.0 to 3.6 V Supply
0 7 CC
CE Chip Enable V Ground
SS
OE Output Enable NC No Connect
Doc. No. MD-1071, Rev. E 2009 SCILLC. All rights reserved.
2
Characteristics subject to change without notice
I/O A
1 7
I/O A
2 12
V A
SS 14
NC NC
I/O V
3 CC
I/O WE
4
I/O A
5 13