CAT34C02 2 2 kb I C EEPROM for DDR2 DIMM Serial Presence Detect Description CAT34C02 Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit Operating Temperature 45 to +130 C Storage Temperature 65 to +150 C Voltage on Any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V Voltage on Pin A with Respect to Ground 0.5 to +10.5 V 0 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than 0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may CC undershoot to no less than 1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns. CC Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter Min Units N (Note 3) Endurance 1,000,000 Program/ Erase Cycles END T Data Retention 100 Years DR 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 3. Page Mode, V = 5 V, 25C CC Table 3. D.C. OPERATING CHARACTERISTICS (V = 1.7 V to 5.5 V, T = 40C to +85C, unless otherwise specified.) CC A Symbol Parameter Test Conditions Min Max Units I Supply Current V < 3.6 V, f = 100 kHz 1 mA CC CC SCL V > 3.6 V, f = 400 kHz 2 CC SCL I Standby Current All I/O Pins at GND or V T = 40C to +85C 1 A SB CC A V 3.3 V CC T = 40C to +85C 3 A V > 3.3 V CC I I/O Pin Leakage Pin at GND or V 2 A L CC V Input Low Voltage 0.5 0.3 x V V IL CC V Input High Voltage 0.7 x V V + 0.5 IH CC CC V Output Low Voltage V > 2.5 V, I = 3 mA 0.4 OL CC OL V < 2.5 V, I = 1 mA 0.2 CC OL Table 4. PIN IMPEDANCE CHARACTERISTICS (V = 1.7 V to 5.5 V, T = 40C to +85C, unless otherwise specified.) CC A Symbol Parameter Conditions Max Units C (Note 4) SDA I/O Pin Capacitance V = 0 V, f = 1.0 MHz, V = 5.0 V 8 pF IN IN CC Other Input Pins 6 I (Note 5) WP Input Current V < V , V = 5.5 V 130 A WP IN IH CC V < V , V = 3.6 V 120 IN IH CC V < V , V = 1.7 V 80 IN IH CC V > V 2 IN IH I (Note 5) Address Input Current V < V , V = 5.5 V 50 A A IN IH CC (A0, A1, A2) V < V , V = 3.6 V 35 IN IH CC Product Rev H V < V , V = 1.7 V 25 IN IH CC V > V 2 IN IH 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pull-down reverts to a weak current CC source.