CAT9534WI-GT2 ON Semiconductor

CAT9534 2 8-bit I C and SMBus I/O Port with Interrupt Description 2 The CAT9534 is an 8bit parallel input/output port expander for I C and SMBus compatible applications. These I/O expanders provide a CAT9534 A0 I/O 0 A1 I/O 1 A2 I/O 2 8 BIT SCL I/O 2 INPUT/ INPUT 3 I C/SMBUS FILTER OUTPUT SDA CONTROL I/O 4 WRITE pulse PORTS I/O 5 READ pulse V CC I/O 6 I/O POWERON 7 V CC RESET V SS LP FILTER INT Note: All I/Os are set to inputs at RESET. Figure 1. Block Diagram Table 1. PIN DESCRIPTION SOIC / TSSOP TQFN Pin Name Function 1 15 A0 Address Input 0 2 16 A1 Address Input 1 3 1 A2 Address Input 2 4 7 2 5 I/O Input/Output Port 0 to Input/Output Port 3 0 3 8 6 V Ground SS 9 12 7 10 I/O Input/Output Port 4 to Input/Output Port 7 4 7 13 11 INT Interrupt Output (open drain) 14 12 SCL Serial Clock 15 13 SDA Serial Data 16 14 V Power Supply CC Table 2. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units V with Respect to Ground 0.5 to +6.5 V CC Voltage on Any Pin with Respect to Ground 0.5 to +5.5 V DC Current on I/O to I/O 50 mA 0 7 DC Input Current 20 mA V Supply Current 85 mA CC V Supply Current 100 mA SS Package Power Dissipation Capability (T = 25C) 1.0 W A Junction Temperature +150 C Storage Temperature 65 to +150 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min Units V (Note 1) ESD Susceptibility JEDEC Standard JESD 22 2000 Volts ZAP I (Notes 1, 2) Latch up JEDEC Standard 17 100 mA LTH 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latchup protection is provided for stresses up to 100 mA on address and data pins from 1 V to V +1 V. CC