CD4051BC CD4052BC CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer Dual 4-Channel Analog
Multiplexer/Demultiplexer Triple 2-Channel Analog Multiplexer/Demultiplexer
November 1983
Revised April 2002
CD4051BC CD4052BC CD4053BC
Single 8-Channel Analog Multiplexer/Demultiplexer
Dual 4-Channel Analog Multiplexer/Demultiplexer
Triple 2-Channel Analog Multiplexer/Demultiplexer
General Description Features
The CD4051BC, CD4052BC, and CD4053BC analog mul- Wide range of digital and analog signal levels:
tiplexers/demultiplexers are digitally controlled analog digital 3 15V, analog to 15V
p-p
switches having low ON impedance and very low OFF
Low ON resistance: 80 (typ.) over entire 15V
p-p
leakage currents. Control of analog signals up to 15V
p-p
signal-input range for V V = 15V
DD EE
can be achieved by digital signal amplitudes of 315V. For
High OFF resistance:
example, if V = 5V, V = 0V and V = 5V, analog sig-
DD SS EE
channel leakage of 10 pA (typ.) at V V = 10V
DD EE
nals from 5V to +5V can be controlled by digital inputs of
05V. The multiplexer circuits dissipate extremely low qui- Logic level conversion for digital addressing signals of
escent power over the full V V and V V supply 3 15V (V V = 3 15V) to switch analog signals
DD SS DD EE DD SS
voltage ranges, independent of the logic state of the control to 15 V (V V = 15V)
p-p DD EE
signals. When a logical 1 is present at the inhibit input ter-
Matched switch characteristics:
minal all channels are OFF.
R = 5 (typ.) for V V = 15V
ON DD EE
CD4051BC is a single 8-channel multiplexer having three
Very low quiescent power dissipation under all
binary control inputs. A, B, and C, and an inhibit input. The
digital-control input and supply conditions:
three binary signals select 1 of 8 channels to be turned
1 W (typ.) at V V = V V = 10V
DD SS DD EE
ON and connect the input to the output.
Binary address decoding on chip
CD4052BC is a differential 4-channel multiplexer having
two binary control inputs, A and B, and an inhibit input. The
two binary input signals select 1 or 4 pairs of channels to
be turned on and connect the differential analog inputs to
the differential outputs.
CD4053BC is a triple 2-channel multiplexer having three
separate digital control inputs, A, B, and C, and an inhibit
input. Each control input selects one of a pair of channels
which are connected in a single-pole double-throw configu-
ration.
Ordering Code:
Order Number Package Number Package Description
CD4051BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4051BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4051BCMTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
CD4051BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD4052BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4052BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4052BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD4053BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4053BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4053BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
2002 Fairchild Semiconductor Corporation DS005662 www.fairchildsemi.comConnection Diagrams
Pin Assignments for DIP and SOIC
CD4051BC CD4052BC
CD4053BC
Truth Table
INPUT STATES ON CHANNELS
INHIBIT C B A CD4051B CD4052B CD4053B
0 0 0 0 0 0X, 0Y cx, bx, ax
0 0 0 1 1 1X, 1Y cx, bx, ay
0 0 1 0 2 2X, 2Y cx, by, ax
0 0 1 1 3 3X, 3Y cx, by, ay
0 1 0 0 4 cy, bx, ax
0 1 0 1 5 cy, bx, ay
0 110 6 cy, by, ax
0 111 7 cy, by, ay
1 * * * NONE NONE NONE
*Dont Care condition.
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CD4051BC CD4052BC CD4053BC