ESD5205 ESD Protection Diodes Low Capacitance ESD Protection Diode for High Speed Data Line The ESD5205 surge protection is designed to protect high speed www.onsemi.com data lines from ESD. Low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high MARKING speed data lines. DIAGRAM Features Protection for the Following IEC Standards: SOT963 XM CASE 527AD IEC 6100042 (Level 4) 1 Low ESD Clamping Voltage This is a PbFree Device X = Specific Device Code M = Month Code Typical Applications SD Connector PIN CONFIGURATION MAXIMUM RATINGS (T = 25C unless otherwise noted) AND SCHEMATIC J Rating Symbol Value Unit Peak Power Dissipation, P 18 W 1 6 PK 8 x 20 s Operating Junction Temperature Range T 55 to +125 C 2 5 J Storage Temperature Range T 55 to +150 C stg 3 4 Lead Solder Temperature T 260 C L Maximum (10 Seconds) IEC 6100042 Contact (ESD) ESD 15 kV IEC 6100042 Air (ESD) ESD 15 kV ORDERING INFORMATION Stresses exceeding those listed in the Maximum Ratings table may damage the Device Package Shipping device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ESD5205P6T6G SOT963 8000 / Tape & (PbFree) Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. See Application Note AND8308/D for further description of survivability specs. Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: September, 2017 Rev. 1 ESD5205/DESD5205 ELECTRICAL CHARACTERISTICS (T = 25C unless otherwise specified) A Parameter Symbol Conditions Min Typ Max Unit Reverse Working Voltage V I/O Pin to GND 5.0 V RWM Breakdown Voltage V I = 1 mA, I/O Pin to GND 5.5 V BR T Reverse Leakage Current I V = 5 V, I/O Pin to GND 1.0 A R RWM Clamping Voltage (Note 1) V I = 1 A, I/O Pin to GND (8 x 20 s pulse) 9 V C PP I = 2 A, I/O Pin to GND (8 x 20 s pulse) 10 PP Clamping Voltage (Note 2) V IEC6100042, 8 KV Contact See Figures 1 and 2 V C Clamping Voltage V I = 8 A 11.4 C PP TLP (Note 3) I = 16 A 15.6 PP I = 8 A 4.5 PP I = 16 A 8.1 PP Junction Capacitance C V = 0 V, f = 1 MHz between I/O Pins and GND 9.0 pF J R 1. Surge current waveform per Figure 5. 2. For test procedure see Figures 3 and 4 and application note AND8307/D. 3. ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z = 50 , t = 100 ns, t = 4 ns, averaging window t = 30 ns to t = 60 ns. 0 p r 1 2 Figure 1. IEC61000 42 +8 KV Contact ESD Figure 2. IEC6100042 8 KV Contact Clamping Voltage Clamping Voltage www.onsemi.com 2