2 A Low-Voltage PMOS-NMOS Bridge Driver FAN3268 Description The FAN3268 dual 2 A gate driver is optimized to drive a highside Pchannel MOSFET and a lowside Nchannel MOSFET in motor www.onsemi.com control applications operating from a voltage rail up to 18 V. The driver has TTL input thresholds and provides buffer and level translation functions from logic inputs. Internal circuitry provides an undervoltage lockout function that prevents the output switching devices from operating if the V supply voltage is below the DD operating level. Internal 100 k resistors bias the noninverting SOIC8 output low and the inverting output to V to keep the external DD CASE 751EB MOSFETs off during startup intervals when logic control signals may not be present. MARKING DIAGRAM The FAN3268 driver incorporates MillerDrive architecture for the final output stage. This bipolarMOSFET combination provides high current during the Miller plateau stage of the MOSFET turnon / turn off process to minimize switching loss, while providing 3268T railtorail voltage swing and reverse current capability. ALYW The FAN3268 has two independent enable pins that default to on if not connected. If the enable pin for non inverting channel A is pulled low, OUTA is forced low if the enable pin for inverting channel B is pulled low, OUTB is forced high. If an input is left unconnected, 3268T = Specific Device Code internal resistors bias the inputs such that the external MOSFETs are A = Assembly Site off. L = Wafer Lot Number YW = Assembly Start Week Features 4.5 V to 18 V Operating Range ORDERING INFORMATION Drives HighSide PMOS and LowSide NMOS in Motor Control or See detailed ordering and shipping information on page 13 of this data sheet. Buck StepDown Applications Inverting Channel B Biases HighSide PMOS Device Off (with Internal 100 k Resistor) when V is below UVLO Threshold DD TTL Input Thresholds 2.4 A Sink / 1.6 A Source at V = 6 V OUT Internal Resistors Turn Driver Off If No Inputs MillerDrive Technology 8Lead SOIC Package Rated from 40C to +125C Ambient This is a PbFree Device Applications Motor Control with PMOS / NMOS HalfBridge Configuration Buck Converters with HighSide PMOS Device 100% Duty Cycle Operation Possible LogicControlled Load Circuits with HighSide PMOS Switch Related Resources AN6069 Application Review and Comparative Evaluation of LowSide Gate Drivers Semiconductor Components Industries, LLC, 2009 1 Publication Order Number: September, 2020 Rev. 3 FAN3268/DFAN3268 +VRAIL (4.5 18 V) FAN3268 Controller 1 8 ENA ENB 2 A 7 MOTOR 3 GND VDD 6 B 4 5 C BYP Figure 1. Typical Motor Drive Application PACKAGE OUTLINE 1 8 ENA ENB 2 INA 7 OUTA 3 6 GND VDD 4 5 INB OUTB Figure 2. Pin Configuration (Top View) THERMAL CHARACTERISTICS (Note 1) Package (Note 2) (Note 3) (Note 4) (Note 5) (Note 6) Units JL JL JL JL JL 8Pin Small Outline Integrated Circuit (SOIC) 40 31 89 43 3 C/W 1. Estimates derived from thermal simulation actual values depend on the application. 2. Theta JL ( ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) JL that are typically soldered to a PCB. 3. Theta JT ( ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform JT temperature by a top side heatsink. 4. Theta JA ( ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given JA is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD512, JESD515, and JESD517, as appropriate. 5. Psi JB ( ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application JB circuit board reference point for the thermal environment defined in Note 4. For the SOIC8 package, the board reference is defined as the PCB copper adjacent to pin 6. 6. Psi JT ( ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of JT the top of the package for the thermal environment defined in Note 4. www.onsemi.com 2