FDS8949 F085 Dual N-Channel Logic Level PowerTrench MOSFET February 2010 FDS8949 F085 tm Dual N-Channel Logic Level PowerTrench MOSFET 40V, 6A, 29m Features General Description These N-Channel Logic Level MOSFETs are produced Max r = 29m at V = 10V DS(on) GS using Fairchild Semiconductors advanced Max r = 36m at V = 4.5V DS(on) GS PowerTrench process that has been especially tailored Low gate charge to minimize the on-state resistance and yet maintain superior switching performance. High performance trench technology for extremely low These devices are well suited for low voltage and r DS(on) battery powered applications where low in-line power High power and current handling capability loss and fast switching are required. Qualified to AEC Q101 Applications RoHS compliant Inverter Power suppliers D2 D2 D1 D1 G2 SO-8 S2 G1 S1 Pin 1 MOSFET Maximum Ratings T = 25C unless otherwise noted A Symbol Parameter Ratings Units V Drain to Source Voltage 40 V DS V Gate to Source Voltage 20 V GS Drain Current -Continuous (Note 1a) 6 I A D -Pulsed 20 E Drain-Source Avalanche Energy (Note 3) 26 mJ AS Power Dissipation for Dual Operation 2 P 1.6 W Power Dissipation for Single Operation (Note 1a) D (Note 1b) 0.9 T , T Operating and Storage Junction Temperature Range -55 to 150 C J STG Thermal Characteristics R Thermal Resistance-Single operation, Junction to Ambient (Note 1a) 81 JA R Thermal Resistance-Single operation, Junction to Ambient (Note 1b) 135 C/W JA R Thermal Resistance, Junction to Case (Note 1) 40 JC Package Marking and Ordering Information Device Marking Device Reel Size Tape Width Quantity FDS8949 FDS8949 F085 13 12mm 2500 units 2010 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDS8949 F085 Rev. A FDS8949 F085 Dual N-Channel Logic Level PowerTrench MOSFET Electrical Characteristics T = 25C unless otherwise noted J Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BV Drain to Source Breakdown Voltage I = 250A, V = 0V 40 V DSS D GS BV Breakdown Voltage Temperature DSS I = 250A, referenced to 25C 33 mV/C D T Coefficient J V = 32V, V = 0V 1 A DS GS I Zero Gate Voltage Drain Current DSS T = 55C 10 A J I Gate to Source Leakage Current V = 20V,V = 0V 100 nA GSS GS DS On Characteristics (Note 2) V Gate to Source Threshold Voltage V = V , I = 250A 1 1.9 3 V GS(th) GS DS D V Gate to Source Threshold Voltage GS(th) I = 250A, referenced to 25C -4.6 mV/C D T Temperature Coefficient J V = 10V, I = 6A 21 29 GS D r Drain to Source On Resistance V = 4.5V, I = 4.5A 26 36 m DS(on) GS D V = 10V, I = 6A,T = 125C 29 43 GS D J g Forward Transconductance V = 10V,I = 6A 22 S FS DS D Dynamic Characteristics C Input Capacitance 715 955 pF iss V = 20V, V = 0V, DS GS C Output Capacitance 105 140 pF oss f = 1MHz C Reverse Transfer Capacitance 60 90 pF rss R Gate Resistance f = 1MHz 1.1 g Switching Characteristics t Turn-On Delay Time 9 18 ns d(on) V = 20V, I = 1A DD D t Rise Time 5 10 ns r V = 10V, R = 6 GS GEN t Turn-Off Delay Time 23 37 ns d(off) t Fall Time 3 6 ns f Q Total Gate Charge 7.7 11 nC g Q Gate to Source Gate Charge V = 20V, I = 6A,V = 5V 2.4 nC gs DS D GS Q Gate to Drain MillerCharge 2.8 nC gd Drain-Source Diode Characteristics and Maximum Ratings V Source to Drain Diode Forward Voltage V = 0V, I = 6A (note 2) 0.8 1.2 V SD GS S t Reverse Recovery Time (note 3) 17 26 ns rr I = 6A, d /d = 100A/s F iF t Q Reverse Recovery Charge 7 11 nC rr Notes: 1: R is the sum of the junction-to-case and case-to- ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the JA drain pins. R is guaranteed by design while R is determined by the users board design. JC JA a) 81C/W when b) 135C/W when mounted on a 2 mounted on a 1in minimum pad . pad of 2 oz copper Scale 1:1 on letter size paper 2: Pulse Test: Pulse Width < 300 us, Duty Cycle < 2.0%. 3: Starting T = 25C, L = 1mH, I = 7.3A, V = 40V, V = 10V. J AS DD GS FDS8949 F085 Rev. A 2 www.fairchildsemi.com