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Based on the TRUESENSE 5.5 micron Interline Transfer CCD Platform, the sensor features broad dynamic www.onsemi.com range, excellent imaging performance, and a flexible readout architecture that enables use of 1, 2, or 4 outputs for full resolution readout up to 8 frames per second. A vertical overflow drain structure suppresses image blooming and enables electronic shuttering for precise exposure control. The sensor is available with the TRUESENSE Sparse Color Filter Pattern, a technology which provides a 2x improvement in light sensitivity compared to a standard color Bayer part. The sensor shares common PGA pin out and electrical configurations with other devices based on the TRUESENSE 5.5 micron Interline Transfer CCD Platform, allowing a single camera design to be leveraged to support multiple members of this sensor family. Figure 1. KAI16050 CCD Image Sensor Table 1. GENERAL SPECIFICATIONS Parameter Typical Value Architecture Interline CCD Progressive Scan Features Total Number of Pixels 4964 (H) x 3332 (V) Bayer Color Pattern, TRUESENSE Sparse Number of Effective Pixels 4920 (H) x 3288 (V) Number of Active Pixels 4896 (H) x 3264 (V) Color Filter Pattern, and Monochrome Pixel Size 5.5 m (H) x 5.5 m (V) Configurations Active Image Size 26.93 mm (H) x 17.95 mm (V) Progressive Scan Readout 32.36 mm (diag.) APSH Format Flexible Readout Architecture Aspect Ratio 3:2 Number of Outputs 1, 2, or 4 High Frame Rate Charge Capacity 20,000 electrons High Sensitivity Output Sensitivity 34 V/e Low Noise Architecture Quantum Efficiency Excellent Smear Performance Pan (AXA, QXA, PXA) 43% R, G, B (FXA, QXA) 28%, 35%, 38% Package Pin Reserved for Device R, G, B (CXA, PXA) 29%, 35%, 37% Identification Read Noise (f = 40 MHz) 12 electrons rms Dark Current Photodiode 2 electrons/s Applications VCCD 140 electrons/s Industrial Imaging and Inspection Dark Current Doubling Temp. Photodiode 7C Traffic VCCD 9C Security Dynamic Range 64 dB Charge Transfer Efficiency 0.999999 Blooming Suppression > 300 X Smear Estimated 100 dB ORDERING INFORMATION See detailed ordering and shipping information on page 2 of Image Lag < 10 electrons this data sheet. Maximum Pixel Clock Speed 40 MHz Maximum Frame Rates Quad Output 8 fps Dual Output 4 fps Single Output 2 fps Package 72 pin PGA Cover Glass AR coated, 2 Sides NOTE: All parameters are specified at T = 40C unless otherwise noted. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: August, 2015 Rev. 7 KAI16050/D