Ordering number : EN6086 CMOS IC LC75884E, LC75884W 1/4 Duty LCD Display Drivers with Key Input Function Overview Package Dimensions The LC75884E and LC75884W are 1/4 duty LCD display unit: mm drivers that can directly drive up to 220 segments and can QFP80E control up to four general-purpose output ports. These LC75884E products also incorporate a key scan circuit that accepts 23.2 input from up to 30 keys to reduce printed circuit board 1.6 20.0 0.8 0.8 0.35 0.15 wiring. 64 41 65 40 Features Key input function for up to 30 keys (A key scan is performed only when a key is pressed.) 1/4duty - 1/2bias and 1/4duty - 1/3bias drive schemes 25 80 can be controlled from serial data (up to 220 segments). 124 Sleep mode and all segments off functions that are 2.7 controlled from serial data. 21.6 0.8 Segment output port/general-purpose output port SANYO: QFP80E(QIP80E) function switching that is controlled from serial data. Serial data I/O supports CCB format communication unit: mm with the system controller. SQFP80 Direct display of display data without the use of a LC75884W decoder provides high generality. 14.0 0.135 12.0 Independent V for the LCD driver block (V can LCD LCD 1.25 0.5 1.25 be set to in the range V -0.5 to 6.0 volts.) 60 41 DD Provision of an on-chip voltage-detection type reset 61 40 circuit prevents incorrect displays. RES pin provided for forcibly initializing the IC internal circuits. RC oscillator circuit. 21 80 120 0.2 CCB is a trademark of SANYO ELECTRIC CO., LTD. CCB is SANYOs original bus format and all the bus addresses are controlled by SANYO. 0.5 0.5 SANYO: SQFP80 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircrafts control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 22299RM (OT) No. 6086-1/27 17.2 1.6 14.0 1.0 14.0 0.8 12.0 1.25 1.25 0.5 0.1 1.4 1.6max 3.0max 0.8 15.6LC75884E, LC75884W Specifications Absolute Maximum Ratings at Ta=25C, V =0V SS Parameter Symbol Conditions Ratings Unit V max V 0.3 to +7.0 V DD DD Maximum supply voltage V max V 0.3 to +7.0 LCD LCD V 1 CE, CL, DI, RES 0.3 to +7.0 IN Input voltage V 2 OSC,TEST 0.3 to V +0.3 V IN DD V 3 V 1, V 2, KI1 to KI5 0.3 to V +0.3 IN LCD LCD LCD V 1 DO -0.3 to +7.0 OUT Output voltage V 2 OSC 0.3 to V +0.3 V OUT DD V 3 S1 to S55, COM1 to COM4, KS1 to KS6, P1 to P4 0.3 to V +0.3 OUT LCD I 1 S1 to S55 300 A OUT I 2 COM1 to COM4 3 OUT Output current I 3 KS1 to KS6 1 mA OUT I 4 P1 to P4 5 OUT Allowable power dissipation Pd max Ta = 85C 200 mW Operating temperature Topr 40 to +85 C Storage temperature Tstg 55 to +125 C Allowable Operating Ranges at Ta = 40 to +85C, V =0V SS Ratings Parameter Symbol Conditions Unit min typ max V V 4.5 6.0 DD DD Supply voltage V V V V 0.5 6.0 LCD LCD DD V 1 V 1 2/3 V V LCD LCD LCD LCD Input voltage V V 2 V 2 1/3 V V LCD LCD LCD LCD V 1 CE, CL, DI, RES 0.8 V 6.0 IH DD Input high level voltage V V 2 KI1 to KI5 0.6 V V IH DD LCD Input low level voltage V CE, CL, DI, RES, KI1 to KI5 0 0.2 V V IL DD Recommended external resistance R OSC 43 k OSC Recommended external capacitance C OSC 680 pF OSC Guaranteed oscillator range f OSC 25 50 100 kHz OSC Data setup time t CL, DI :Figure 2 160 ns ds Data hold time t CL, DI :Figure 2 160 ns dh CE wait time t CE, CL :Figure 2 160 ns cp CE setup time t CE, CL :Figure 2 160 ns cs CE hold time t CE, CL :Figure 2 160 ns ch High level clock pulse width t CL :Figure 2 160 ns H Low level clock pulse width t CL :Figure 2 160 ns L Rise time t CE, CL, DI :Figure 2 160 ns r Fall time t CE, CL, DI :Figure 2 160 ns f DO output delay time t DO R =4.7k, C =10pF *1 :Figure 2 1.5 s dc PU L DO rise time t DO R =4.7k, C =10pF *1 :Figure 2 1.5 s dr PU L Note: *1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor R and the load capacitance C . PU L No. 6086-2/27