LE25U81AQETXG ON Semiconductor

Ordering number : ENA2199 LE25U81AQE CMOS LSI LE25U81AQE Figure 2 Block Diagram 8M Bit X- Flash EEPROM DECODER ADDRESS Cell Array BUFFERS & LATCHES Y-DECODER I/O BUFFERS CONTROL & LOGIC DATA LATCHES SERIAL INTERFACE CS SI/SIO0 SO/SIO1 WP SCK HOLD Table 1 Pin Description Symbol Pin Name Description SCK Serial clock This pin controls the data input/output timing. The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is output synchronized to the falling edge of the serial clock. SI/SIO0 Serial data input The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the / Serial data input output serial clock. It changes into the output pin at Dual Output and it changes into the input output pin at Dual I/O. SO/SIO1 Serial data input The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock. / Serial data input output It changes into the output pin at Dual Output and it changes into the input output pin at Dual I/O. CS Chip select The device becomes active when the logic level of this pin is low it is deselected and placed in standby status when the logic level of the pin is high. WP Write protect The status register write protect (SRWP) takes effect when the logic level of this pin is low. HOLD Hold Serial communication is suspended when the logic level of this pin is low. V Power supply This pin supplies the 2.3 to 2.7V supply voltage. DD V Ground This pin supplies the 0V supply voltage. SS No.A2199-2/22