MC100EP131FAR2G ON Semiconductor

MC10EP131, MC100EP131 3.3V / 5VECL Quad D FlipFlop with Set, Reset, and Differential Clock Description MC10EP131, MC100EP131 Q Q Q Q Q Q Q Q 3 3 2 2 1 1 0 0 D2 SET R3 D3 V C3 C3 V EE CC 32 31 30 29 28 27 26 25 R2 1 24 Q3 24 23 22 21 20 19 18 17 25 16 V V CC CC 2 23 C2 Q3 26 15 C R 3 0 3 22 Q2 C2 27 14 C D 3 0 CC 4 21 Q2 MC10EP131 28 13 MC100EP131 V V EE CC CC 5 20 Q1 32 Lead LQFP Pinout 29 12 D C (Top View) 3 0 C1 6 19 Q1 30 11 R C 7 3 0 C1 18 Q0 31 10 SET R D1 8 17 Q0 1 32 9 9 10 11 12 13 14 15 16 D V 2 EE 123 4567 8 V C0 V D0 R0 V R1 C0 EE CC CC Figure 2. 32Lead QFN Pinout (Top View) R C C C C C C D 2 2 2 C C 1 1 1 S Warning: All V and V pins must be externally connected CC EE Q D to Power Supply to guarantee proper operation. D Q 3 3 C Figure 1. 32Lead LQFP Pinout (Top View) 3 Q Q C 3 3 R Table 1. PIN DESCRIPTION R 3 PIN FUNCTION D * ECL Data Inputs S 03 D Q Q 2 D 2 C *, C * ECL Separate Clock Inputs 03 03 C 2 C *, C * ECL Common Clock Inputs C C C Q Q 2 2 R * ECL Asynchronous Reset R 03 R 2 SET* ECL Asynchronous Set Q , Q ECL Data Outputs 03 03 SET V Positive Supply CC C C V Negative Supply EE C C EP for The Exposed Pad (EP) on the QFN32, only QFN32 package bottom is thermally connected to the die R 1 for improved heat transfer out R C of package. The exposed pad 1 Q Q 1 must be attached to a heat C 1 sinking conduit. The pad is electrically connected to V . EE D Q 1 1 Q D S * Pins will default LOW when left open. R 0 Table 2. TRUTH TABLE R C D S* R* CLK Q 0 Q Q 0 C 0 L L L Z L H L L Z H D Q Q X H L X H 0 0 D S X L H X L X H H X Undef V EE Z = LOW to HIGH Transition Figure 3. Logic Diagram * Pins will default low when left open.