MC100EP16VC
3.3V / 5VECL Differential
Receiver/Driver with High
Gain and Enable Output
Description
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The EP16VC is a differential receiver/driver. The device is
functionally equivalent to the EP16 and LVEP16 devices but with high
gain and enable output.
8
8
The EP16VC provides an EN input which is synchronized with the
1
1
data input (D) signal in a way that provides glitchless gating of the
SOIC8NB TSSOP8
QHG and QHG outputs.
DFN8
D SUFFIX DT SUFFIX
When the EN signal is LOW, the input is passed to the outputs and
MN SUFFIX
CASE CASE
the data output equals the data input. When the data input is HIGH and CASE 506AA
75107 948R02
EN goes HIGH, it will force the Q LOW and the Q HIGH on the
HG HG
next negative transition of the data input. If the data input is LOW
when the EN goes HIGH, the next data transition to a HIGH is ignored
MARKING DIAGRAMS*
and Q remains LOW and Q remains HIGH. The next positive
HG HG
transition of the data input is not passed on to the data outputs under
these conditions. The Q and Q outputs remain in their disabled
HG HG
8
8
state as long as the EN input is held HIGH. The EN input has no
KEP66
influence on the Q output and the data input is passed on (inverted) to KP66
ALYW
ALYW
this output whether EN is HIGH or LOW. This configuration is ideal
14
for crystal oscillator applications where the oscillator can be free
1
1
running and gated on and off synchronously without adding extra
counts to the output.
A = Assembly Location
The V /D pin is internally dedicated and available for differential
L = Wafer Lot
BB
Y = Year
interconnect. V /D may rebias AC coupled inputs. When used,
BB
W = Work Week
decouple V /D and V via a 0.01F capacitor and limit current
BB CC
M = Date Code
sourcing or sinking to 1.5 mA. When not used, V /D should be left
BB
= Pb-Free Package
open.
The 100 Series contains temperature compensation. (Note: Microdot may be in either location)
Features
*For additional marking information, refer to
Application Note AND8002/D.
310 ps Typical Prop Delay Q,
380 ps Typical Prop Delay QHG, QHG
Gain > 200
ORDERING INFORMATION
Maximum Frequency > 3 GHz Typical
Device Package Shipping
PECL Mode Operating Range:
MC100EP16VCDG SOIC8NB 98 Units/Tube
V = 3.0 V to 5.5 V with V = 0 V
CC EE
(Pb-Free)
NECL Mode Operating Range:
MC100EP16VCDR2G SOIC8NB 2500/Tape & Reel
V = 0 V with V = 3.0 V to 5.5 V
CC EE
(Pb-Free)
Open Input Default State
MC100EP16VCDTG TSSOP8 100 Units/Tube
Q Output Will Default LOW with D Inputs Open or at V
HG EE (Pb-Free)
V Output
BB MC100EP16VCDTR2G TSSOP8 2500/Tape & Reel
(Pb-Free)
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
MC100EP16VCMNR4G DFN8 1000/Tape & Reel
(Pb-Free)
For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2016
1 Publication Order Number:
August, 2016 Rev. 8 MC10EP16VC/D
3G M
MC100EP16VC
Table 1. PIN DESCRIPTION
Q 1 8 V
CC
Pin Function
D* ECL Data Input
Q ECL Data Output
D 2 7 Q
HG
Q , Q ECL High Gain Data Outputs
HG HG
EN* ECL Enable Input
V /D Reference Voltage Output / ECL Data Input
BB
3 6 Q
V Positive Supply
HG CC
V /D
BB
V Negative Supply
EE
OE
Q
LEN
EP (DFN8 only) Thermal exposed pad must be
V
connected to a sufficient thermal conduit. Elec-
BB
LATCH
trically connect to the most negative supply
45 V
EN EE
(GND) or leave unconnected, floating open.
D
*Pins will default LOW when left open.
Figure 1. 8-Lead Pinout (Top View) and Logic
Diagram
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor N/A
ESD Protection
Human Body Model > 4 kV
Machine Model > 200 V
Charged Device Model > 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg
SOIC8NB Level 1
TSSOP8 Level 3
DFN8 Level 1
Flammability Rating UL 94 V0 @ 0.125 in
Oxygen Index: 28 to 34
Transistor Count 167 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2