MC100EPT26 3.3 V1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator Description www.onsemi.com The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead 8 8 package and the 1:2 fanout design of the EPT26 makes it ideal for 1 1 applications which require the low skew duplication of a signal in a tightly packed PC board. SOIC8 NB TSSOP8 DFN8 D SUFFIX DT SUFFIX MN SUFFIX The V output allows the EPT26 to be used in a Single-Ended BB CASE 75107 CASE 948R02 CASE 506AA input mode. In this mode the V output is tied to the D0 input for a BB non-inverting buffer or the D0 input for an inverting buffer. If used, the V pin should be bypassed to ground with > 0.01 F capacitor. BB MARKING DIAGRAMS* For a Single-Ended direct connection, use an external voltage reference source such as a resistor divider. Do not use V for a BB 8 8 Single-Ended direct connection or port to another device. 1 KPT26 3W M KA26 ALYW ALYW 4 Features 1 1 1.4 ns Typical Propagation Delay Maximum Frequency = > 275 MHz Typical SOIC8 NB TSSOP8 DFN8 The 100 Series Contains Temperature Compensation A = Assembly Location Operating Range: V = 3.0 V to 3.6 V with GND = 0 V CC L = Wafer Lot Y = Year 24 mA TTL outputs W = Work Week Q Outputs Will Default LOW with Inputs Open or at V EE M = Date Code = Pb-Free Package V Output BB (Note: Microdot may be in either location) These Devices are Pb-Free, Halogen Free and are RoHS Compliant *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC100EPT26DG SOIC8 NB 98 Units/Tube (Pb-Free) MC100EPT26DR2G SOIC8 NB 2500 Tape & Reel (Pb-Free) MC100EPT26DTG TSSOP8 100 Tape & Reel (Pb-Free) MC100RPT26DTR2G 2500 Tape & Reel TSSOP8 (Pb-Free) MC100EPT26MNR4G DFN8 1000 Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: August, 2016 Rev. 17 MC100EPT26/DMC100EPT26 Table 1. PIN DESCRIPTION NC 1 8 V CC Pin Function Q0, Q1 LVTTL Outputs D0**, D1** Differential LVPECL Inputs Pair D 2 7 Q0 V Positive Supply CC LVTTL V Output Reference Voltage BB D 3 6 Q1 GND Ground NC No Connect EP (DFN8 only) Thermal exposed pad must be con- nected to a sufficient thermal conduit. Electric- V45LVPECL GND BB ally connect to the most negative supply (GND) or leave unconnected, floating open. ** Pins will default to V /2 when left open. CC (Top View) Figure 1. 8-Lead Pinout and Logic Diagram Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 50 k Internal Input Pullup Resistor 50 k ESD Protection Human Body Model > 1.5 kV Machine Model > 100 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC8 NB Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 117 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2