MC100LVEP05DR2G ON Semiconductor

MC100LVEP05 2.5V / 3.3V ECL 2-Input Differential AND/NAND Description The MC100LVEP05 is a 2input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 MC100LVEP05 Table 1. PIN DESCRIPTION 1 8 Pin Function D V 0 CC D0*, D1*, D0**, D1** ECL Data Inputs Q, Q ECL Data Outputs V Positive Supply D Q 2 7 CC 0 V Negative Supply EE EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect 6 D 3 Q 1 to the most negative supply (GND) or leave unconnected, floating open. * Pins will default LOW when left open. ** Pins will default to V /2when left open. CC D45 V 1 EE Table 2. TRUTH TABLE D0 D1 D0 D1 Q Q Figure 1. 8Lead Pinout (Top View) and Logic L L H H L H Diagram L H H L L H H L L H L H H H L L H L Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 37.5 k ESD Protection Human Body Model > 4 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg PbFree Pkg TSSOP8 Level 1 Level 3 DFN8 Level 1 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 167 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.