MC10EP446, MC100EP446 3.3 V/5 V 8Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter Description MC10EP446, MC100EP446 24 23 22 21 20 19 18 17 24 23 22 21 20 19 18 17 25 V 16 V 25 16 CC EE V V CC EE 26 15 V PCLK 26 15 PCLK CF V CF 27 14 27 14 V PCLK V EF PCLK EF 28 13 28 13 V MC10EP446 V V V EE EE CC CC Exposed Pad (EP) MC100EP446 29 12 29 12 SYNC S SYNC S OUT OUT 30 11 SYNC S 30 11 S SYNC OUT OUT 31 10 V 31 10 V V V BB2 CC BB2 CC 32 9 V V 32 9 CC CC V V CC CC 1234 5678 1 2 34 5 6 78 Warning: All V and V pins must be externally connected CC EE to Power Supply to guarantee proper operation. Figure 1. LQFP32 Pinout (Top View) Figure 2. QFN32 Pinout (Top View) Table 1. PIN DESCRIPTION PIN FUNCTION D0*D7* ECL, CMOS, or TTL Parallel Data Input S , S ECL Differential Serial Data Output OUT OUT CLK*, CLK* ECL Differential Clock Input PCLK, PCLK ECL Differential Parallel Clock Output SYNC*, SYNC** ECL Conversion Synchronizing Differential Input (Reset)*** CKSEL* ECL Clock Input Selector CKEN*, CKEN* ECL Clock Enable Differential Input V ECL, CMOS, or TTL Input Selector CF V ECL Reference Mode Connection EF V , V Reference Voltage Output BB1 BB2 V Positive Supply CC V Negative Supply EE * Pins will default LOW when left open. **Pins will default HIGH when left open. ***The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK initiates the conversion process synchronously on the next rising edge of CLK.