Product Information

MC10EP51DTG

MC10EP51DTG electronic component of ON Semiconductor

Datasheet
Flip Flops 3.3V/5V ECL D-Type w/Reset and Diff Clk
Manufacturer: ON Semiconductor
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 6.969 ea
Line Total: USD 6.97

96 - Global Stock
Ships to you between
Tue. 21 May to Thu. 23 May
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
96 - WHS 1


Ships to you between Tue. 21 May to Thu. 23 May

MOQ : 1
Multiples : 1

Stock Image

MC10EP51DTG
ON Semiconductor

1 : USD 6.969
10 : USD 6.486
20 : USD 6.187
50 : USD 6.1755
100 : USD 5.727

82 - WHS 2


Ships to you between Wed. 15 May to Tue. 21 May

MOQ : 2
Multiples : 1

Stock Image

MC10EP51DTG
ON Semiconductor

2 : USD 5.9388
10 : USD 5.82

Read More Specifications

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Circuits
Logic Family
Logic Type
Polarity
Input Type
Output Type
Propagation Delay Time
High Level Output Current
Low Level Output Current
Supply Voltage - Min
Supply Voltage - Max
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Series
Brand
Number Of Input Lines
Number Of Output Lines
Factory Pack Quantity :
Function
Height
Length
Width
Number Of Channels
Cnhts
Hts Code
Mxhts
Operating Supply Voltage
Product Type
Reset Type
Subcategory
Taric
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Additional Infomation About Product

3.3 V/5 VECL D Flip-Flop with Reset and Differential Clock MC10EP51, MC100EP51 Description www.onsemi.com The MC10/100EP51 is a differential clock D flipflop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. 8 8 The reset input is an asynchronous, level triggered signal. Data 1 1 1 enters the master portion of the flipflop when the clock is LOW and is TSSOP8 DFN8 SOIC8 transferred to the slave, and thus the outputs, upon a positive transition DT SUFFIX MN SUFFIX D SUFFIX of the clock. The differential clock inputs of the EP51 allow the device CASE 948R CASE 506AA CASE 751 to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be MARKING DIAGRAMS* pulled down to V and the CLK input will be biased at V /2. EE CC The 100 Series contains temperature compensation. 8 8 Features HP51 1 HEP51 5S M 350 ps Typical Propagation Delay ALYW ALYW Maximum Frequency > 3 GHz Typical 1 1 PECL Mode Operating Range: V = 3.0 V to 5.5 V CC with V = 0 V EE 8 NECL Mode Operating Range: V = 0 V 8 CC KP51 with V = 3.0 V to 5.5 V KEP51 EE ALYW ALYW Open Input Default State Safety Clamp on Inputs 1 1 These Devices are PbFree and are RoHS Compliant H = MC10 K = MC100 5S = MC10 M = Date Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week = PbFree Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: April, 2021 Rev. 11 MC10EP51/DMC10EP51, MC100EP51 Table 1. PIN DESCRIPTION PIN FUNCTION RESET 1 8 V CC CLK*, CLK* ECL Clock Inputs Reset* ECL Asynchronous Reset R D* ECL Data Input D 2 7 Q D Q, Q ECL Data Outputs V Positive Supply CC Flip-Flop V Negative Supply EE CLK 3 6 Q EP (DFN8 only) Thermal exposed pad must be connected to a suf- ficient thermal conduit. Electric- ally connect to the most negative supply (GND) or leave uncon- nected, floating open. CLK45 V EE * Pins will default LOW when left open. Table 2. TRUTH TABLE Figure 1. 8Lead Pinout (Top View) and Logic Diagram D R CLK Q L L Z L H L Z H X H X L Z = LOW to HIGH Transition Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection > 2 kV Human Body Model > 200 V Machine Model > 2 kV Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) PbFree Pkg SOIC8 Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 165 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

ON Semiconductor may also be referenced as

Aptina / ON Semiconductor
FAIRCHILD
FAIRCHILD (ON SEMICONDUCTOR)
Fairchild Semiconductor
FS8
FSC
ON
ON SEMI
ON Semicon
ON SEMICONDUCTOR
ON SEMICONDUCTOR (FAIRCHILD)
ON Semiconductor / Fairchild
ON4
ON5
onsemi
ON-SEMI
onsemi / Fairchild
OOF
Xsens / Fairchild

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