1.8 V/2.5 V/3.3 V Crystal Input to 1:6 LVTTL/LVCMOS Clock Fanout Buffer with OE NB3H83905C www.onsemi.com Description The NB3H83905C is a 1.8 V, 2.5 V or 3.3 V V core Crystal input DD to 1:6 LVTTL/LVCMOS fanout buffer with outputs powered by 16 flexible 1.8 V, 2.5 V, or 3.3 V supply V (with V V ). The DDO DD DDO 1 device accepts a fundamental Parallel Resonant crystal from 3 MHz to 1 40 MHz or a singleended LVCMOS Clock from up to 100 MHz. SOIC16 TSSOP16 QFN20 Two synchronous LVTTL/LVCMOS Enable lines permit D SUFFIX DT SUFFIX MN SUFFIX independent control over outputs BCLK 0:4 and output BCLK5 CASE 751B CASE 948F CASE 485BH enabling or disabling only when the output is in LOW state eliminating potential output glitching or runt pulse generation. When MARKING DIAGRAMS* unused, leave floating open, pins will default to HIGH state. The 6 outputs drive 50 series or parallel terminated transmission 16 16 20 lines. Parallel termination should be to 1/2 V . Series terminated CC 1 NB3H NB3H lines can drive 2 loads each, or 12 lines total. 905C NB3H83905G 83905 Fit, Form, and Function compatible with ICS83905 and PI6C10806. ALYW ALYYWW ALYW Features Six Copies of LVTTL/LVCMOS Output Clock 1 1 Supply Operation V V : DD DDO A = Assembly Location 1.8 V 0.2 V, 2.5 V 5% or 3.3 V 5% Core V DD L = Wafer Lot 1.8 V 0.2 V, 2.5 V 5%, or 3.3 V 5% Output V DDO YY, Y = Year Crystal Oscillator Interface WW, W = Work Week G or = PbFree Package Crystal Input Frequency Range: 3 MHz to 40 MHz (Note: Microdot may be in either location) Clock Input Frequency Range: Up to 100 MHz *For additional marking information, refer to LVCMOS compatible Enable Inputs Application Note AND8002/D. 5 V Tolerant Enable Inputs Low Output to Output Skew: 80 ps Max ORDERING INFORMATION Synchronous Output Enable Device Package Shipping Phase Noise Floor 160 dBc (1 MHz) NB3H83905CDR2G SOIC16 2500 / Industrial Temperature Range (Pb Free) Tape & Reel These are PbFree Devices NB3H83905CDTG TSSOP16 96 Units/ (Pb Free) Tube BCLK0 NB3H83905CDTR2G TSSOP16 2500 / XTAL IN/CLK (Pb Free) Tape & Reel BCLK1 NB3H83905CMNG QFN20 92 Units/ (PbFree) Tube C1 BCLK2 NB3H83905CMNTXG QFN20 3000 / XTAL OUT (PbFree) Tape & Reel BCLK3 C2 For information on tape and reel specifications, BCLK4 including part orientation and tape sizes, please ENABLE1 SYNC refer to our Tape and Reel Packaging Specifications BCLK5 Brochure, BRD8011/D. ENABLE2 SYNC Figure 1. Simplified Block Diagram Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: May, 2021 Rev. 10 NB3H83905C/DNB3H83905C Exposed Pad XTAL OUT 1 16 XTAL IN/CLK 20 19 18 17 16 ENABLE2 2 15 ENABLE1 GND GND 1 15 3 14 BCLK5 BCLK5 V 2 14 GND DDO BCLK0 4 13 V EP DDO 3 13 BCLK4 BCLK0 V 4 12 V 5 12 BCLK4 DDO GND DDO BCLK1 5 11 GND BCLK1 6 11 GND 6 7 8 9 10 GND 7 10 BCLK3 BCLK2 8 9 V DD QFN20 SOIC16/TSSOP16 Figure 2. Pinout Configuration (Top View) Table 1. PIN DESCRIPTION SOIC16 / TSSOP16 QFN20 Name I/O Description 1 19 XTAL OUT Crystal Interface Oscillator Output to drive Crystal 2 20 ENABLE 2 LVTTL / Synchronous Enable Input for BCLK5 Output. Switches only when LVCMOS Input HIGH. Open default condition HIGH due to an internal pullup resistor to V . CC 3, 7, 11 1, 2, 6, 7, GND GND GND Supply pins. All GND, V and V pins must be externally DD DDO 11, 12 connected to power supply to guarantee proper operation. 4, 6, 8, 3, 5, 8, BCLK0, 1, LVCMOS Buffered Clock Outputs 10, 12, 14 10, 13, 15 2, 3, 4, 5 Outputs 5, 13 4, 14 V POWER Positive Supply voltage for outputs. All GND, V and V pins DDO DD DDO must be externally connected to power supply to guarantee proper operation. Bypass with 0.01 F cap to GND. 9 9 V POWER Positive Supply voltage for core. All GND, V and V pins must DD DD DDO be externally connected to power supply to guarantee proper operation. Bypass with 0.01 F cap to GND. 16 NC No Connect 15 17 ENABLE 1 LVTTL / Synchronous Enable Input for BCLK0/1/2/3/4 Output block. Switches LVCMOS Input only when HIGH. Open default condition HIGH due to an internal pullup resistor to V CC 16 18 XTAL IN/ Crystal Interface Oscillator Input from Crystal. Single ended Clock Input. CLK EP The Exposed Pad (EP) on the QFN20 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heatsinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GND on the PC board. www.onsemi.com 2 ENABLE2 GND XTAL OUT GND BCLK2 XTAL IN/CLK V DD ENABLE1 BCLK3 NC