NB3L8504S 2.5 V / 3.3 V 1:4 Differential Input to LVDS Fanout Buffer / Translator Description www.onsemi.com The NB3L8504S is a differential 1:4 LVDS fanout buffer/translator with OE control for each differential output. The differential inputs MARKING which can be driven by either a differential or singleended input, can DIAGRAM* accept various logic level standards such as LVPECL, LVDS, HSTL, 16 HCSL and SSTL. These signals are then translated to four identical LVDS copies of the input up to 700 MHz. As such, the NB3L8504S is TSSOP16 NB3L ideal for Clock distribution applications that require low skew. 16 8504 DT SUFFIX ALYW The NB3L8504S is offered in the TSSOP16 package. CASE 948F 1 Features 1 Four Differential LVDS Outputs A = Assembly Location Each Differential Output has OE Control L = Wafer Lot Y = Year 700 MHz Maximum Output Frequency W = Work Week 660 ps Max Output Rise and Fall Times, LVCMOS = PbFree Package Translates Differential Input to LVDS Levels (Note: Microdot may be in either location) Additive Phase Jitter RMS: < 100 fs Typical *For additional marking information, refer to Application Note AND8002/D. 50 ps Maximum Output Skew 350 ps Maximum Parttopart Skew 1.3 ns Maximum Propagation Delay Operating Range: V = 2.5 V 5% or 3.3 V 10% CC 40C to +85C Ambient Operating Temperature 16Pin TSSOP, 4.4 mm x 5.0 mm x 0.925 mm These are PbFree Devices Applications CLK Telecom CLK Ethernet Networking SONET Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information on page 9 of this data sheet. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: April, 2016 Rev. 2 NB3L8504S/DNB3L8504S Table 1. PIN DESCRIPTIONS AND CHARACTERISTICS Pin Name I/O Description 1 OE0 LVTTL/LVCMOS Input Output Enable pin for Q0, Q0 outputs. Defaults High when left open internal pullup resistor. 2 OE1 LVTTL/LVCMOS Input Output Enable pin for Q1, Q1 outputs. Defaults High when left open internal pullup resistor. 3 OE2 LVTTL/LVCMOS Input Output Enable pin for Q2, Q2 outputs. Defaults High when left open internal pullup resistor. 4 VDD Power 3.3 V / 2.5 V Positive Supply Voltage. 5 GND Power 3.3 V / 2.5 V Negative Supply Voltage. 6 CLK MultiLevel Input Noninverting differential Clock input. Defaults Low when left open internal pulldown resistor. 7 CLK MultiLevel Input Inverting differential Clock input. Defaults to VDD/2 when left open internal pullup and pulldown resistors. 8 OE3 LVTTL/LVCMOS Input Output Enable pin for Q3, Q3 outputs. Defaults High when left open internal pullup resistor. 9 Q3 LVDS Output Inverting differential Clock output. 10 Q3 LVDS Output Noninverting differential Clock output. 11 Q2 LVDS Output Inverting differential Clock output. 12 Q2 LVDS Output Noninverting differential Clock output. 13 Q1 LVDS Output Inverting differential Clock output. 14 Q1 LVDS Output Noninverting differential Clock output. 15 Q0 LVDS Output Inverting differential Clock output. 16 Q0 LVDS Output Noninverting differential Clock output. 1. All VDD and GND pins must be externally connected to a power supply for proper operation. OE0 1 16 Q0 OE1 Q0 2 15 OE2 3 14 Q1 VDD 4 13 Q1 GND 5 12 Q2 CLK 6 11 Q2 CLK 7 10 Q3 OE3 8 9 Q3 Figure 2. NB3L8504S Pinout, 16pin TSSOP (Top View) Table 2. OUTPUT ENABLE FUNCTION TABLE OE 3:0 Outputs Q 0:3 , Q 0:3 LOW High Impedance HIGH (Default) Active www.onsemi.com 2