NB3U1548C 3.3V/2.5V/1.8V/1.5V 160 MHz 1:4 LVCMOS/LVTTL Low Skew Over Voltage Tolerant Fanout Buffer www.onsemi.com Description The NB3U1548C is an LVCMOS, overvoltage tolerant clock fanout MARKING DIAGRAMS buffer targeted for clock generation in high performance telecommunication, networking and computing applications. The 8 8 device is optimized for low skew clock distribution in low voltage 1548C 1 applications. The input overvoltage tolerance enables using this ALYW SOIC8 device in mixed mode voltage applications. An output enable pin D SUFFIX 1 controls whether the outputs are in the active or high impedance state. CASE 751 Guaranteed output skew characteristics make the NB3U1548C ideal for those applications demanding well defined performance and 8 repeatability. The NB3U1548C is packaged in a small SOIC8 and in 8 an TSSOP8 package. 154 1 YWW Features A TSSOP8 DT SUFFIX Low skew 1:4 Fanout Buffer CASE 948S 1 Supports 3.3 V, 2.5 V, 1.8 V and 1.5 V Power Supplies LVCMOS Input and Output Levels A = Assembly Location 3.6 V Overvoltage Tolerance at the Clock and Control Inputs L = Wafer Lot Supports Clock Frequencies up to 160 MHz Y = Year W, WW = Work Week LVCMOS Compatible Control Input for Output Disable = PbFree Package Output Disabled to a High Impedance State (Note: Microdot may be in either location) 40C to 85C Ambient Operating Temperature Available in PbFree RoHS Compliant Packages (SOIC8, TSSOP8) ORDERING INFORMATION See detailed ordering and shipping information on page 9 of These Devices are PbFree and are RoHS Compliant this data sheet. Figure 1. Block Diagram Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: January, 2017 Rev. 4 NB3U1548C/DNB3U1548C CLK IN OE 1 8 2 7 V Q1 DD GND Q2 3 6 Q3 4 5 Q4 Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTIONS Number Name Type Description 1 CLK IN Input Pulldown Singleended clock input. LVCMOS interface levels. 2 Q1 Output Singleended clock output. LVCMOS interface levels. 3 Q2 Output Singleended clock output. LVCMOS interface levels. 4 Q3 Output Singleended clock output. LVCMOS interface levels. 5 Q4 Output Singleended clock output. LVCMOS interface levels. 6 GND Power Power supply ground. 7 VDD Power Power supply pin. 8 OE Input Pullup Output enable pin. See Table 3. LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Min Typ Max Units CIN Input Capacitance 4 pF CPD Power Dissipation Capacitance V = 3.465 V 14 pF DD V = 2.375 V 13 pF DD V = 1.95 V 13 pF DD V = 1.6 V 12 pF DD RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k ROUT Output Impedance V = 3.3 V 5% 9 DD V = 2.5 V 5% 10 DD V = 1.8 V 0.15 V 12 DD V = 1.5 0.1 V 15 DD Function Table Table 3. OE CONFIGURATION TABLE Input OE Operation 0 Q 4:1 disabled (highimpedance) 1 (default) Q 4:1 enabled NOTE: OE is an asynchronous control. www.onsemi.com 2