NB4N527S 3.3V, 2.5Gb/s Dual AnyLevel to LVDS Receiver/Driver/Buffer/ Translator with Internal NB4N527S Exposed Pad (EP) VTD0 D0 D0 VTD0 16 15 14 13 V 1 12 Q0 TD1 2 11 D1 Q0 NB4N527S D1 3 10 Q1 V 4 9 Q1 TD1 56 7 8 GND NC NC V CC Figure 3. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 VTD1 Internal 50 termination pin for D1. (R ) TIN 2 D1 LVPECL, CML, LVDS, Noninverted differential clock/data D1 input (Note 1). LVCMOS, LVTTL, HSTL 3 D1 LVPECL, CML, LVDS, Inverted differential clock/data D1 input (Note 1). LVCMOS, LVTTL, HSTL 4 VTD1 Internal 50 termination pin for D1. (R ) TIN 5 GND 0 V. Ground. 6, 7 NC No connect. 8 V Positive Supply Voltage. CC 9 Q1 LVDS Output Inverted D1 output. Typically loaded with 100 receiver termination resistor across differential pair. 10 Q1 LVDS Output Noninverted D1 output. Typically loaded with 100 receiver termination resistor across differential pair. 11 Q0 LVDS Output Inverted D0 output. Typically loaded with 100 receiver termination resistor across differential pair. 12 Q0 LVDS Output Noninverted D0 output. Typically loaded with 100 receiver termination resistor across differential pair. 13 VTD0 Internal 50 termination pin for D0. 14 D0 LVPECL, CML, LVDS, Noninverted differential clock/data D0 input (Note 1). LVCMOS, LVTTL, HSTL 15 D0 LVPECL, CML, LVDS, Inverted differential clock/data D0 input (Note 1). LVCMOS, LVTTL, HSTL 16 VTD0 Internal 50 termination pin for D0. EP Exposed pad. EP on the package bottom is thermally connected to the die improved heat transfer out of package. The pad is not electrically connected to the die, but is recommended to be soldered to GND on the PCB. 1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to selfoscillation.