NB6L11S 2.5 V 1:2 AnyLevel Input to LVDS Fanout Buffer / Translator The NB6L11S is a differential 1:2 clock or data receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, www.onsemi.com or LVDS. These signals will be translated to LVDS and two identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or MARKING 2.5 Gb/s, respectively. As such, the NB6L11S is ideal for SONET, DIAGRAM* GigE, Fiber Channel, Backplane and other Clock or Data distribution 16 applications. 1 The NB6L11S has a wide input common mode range from NB6L 1 GND + 50 mV to V 50 mV. Combined with the 50 internal CC 11S termination resistors at the inputs, the NB6L11S is ideal for translating ALYW QFN16 a variety of differential or singleended Clock or Data signals to MN SUFFIX CASE 485G 350 mV typical LVDS output levels. The NB6L11S is the 2.5 V version of the NB6N11S and is offered in a small 3 mm X 3 mm 16QFN package. Application notes, models, A = Assembly Location and support documentation are available at www.onsemi.com. L = Wafer Lot Y = Year Features W = Work Week Input Clock Frequency > 2.0 GHz = PbFree Package Input Data Rate > 2.5 Gb/s (Note: Microdot may be in either location) RMS Clock Jitter 0.5 ps, Typical *For additional marking information, refer to Application Note AND8002/D. 622 Mb/s Data Dependent Jitter 6 ps, Typical 380 ps Typical Propagation Delay 120 ps Typical Rise and Fall Times Q0 Single Power Supply V = 2.5 V 5% CC V Q0 TD These are PbFree Devices D D V TD Q1 Q1 Device DDJ = 10 ps Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. TIME (58 ps/div) Figure 2. Typical Output Waveform at 2.488 Gb/s with 231 PRBS 2 (V = 400 mV Input Signal DDJ = 14 ps) INPP Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: November, 2014 Rev. 9 NB6L11S/D VOLTAGE (130 mV/div)NB6L11S Exposed Pad (EP) V V V V CC CC CC CC 16 15 14 13 Q0 1 12 V TD Q0 2 11 D NB6L11S Q1 3 10 D Q1 4 9 V TD 56 7 8 V NC V V CC EE EE Figure 3. NB6L11S Pinout, 16pin QFN (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 Q0 LVDS Output Noninverted D output. Typically loaded with 100 receiver termination resistor across differential pair. 2 Q0 LVDS Output Inverted D output. Typically loaded with 100 receiver termination resistor across differential pair. 3 Q1 LVDS Output Noninverted D output. Typically loaded with 100 receiver termination resistor across differential pair. 4 Q1 LVDS Output Inverted D output. Typically loaded with 100 receiver termination resistor across differential pair. 5 V Positive Supply Voltage. CC 6 NC No Connect. 7 V Negative Supply Voltage. EE 8 V Negative Supply Voltage. EE 9 V Internal 50 termination pin for D. TD 10 D LVPECL, CML, LVDS, Inverted Differential Clock/Data Input (Note 1). LVCMOS, LVTTL 11 D LVPECL, CML, LVDS, Noninverted Differential Clock/Data Input (Note 1). LVCMOS, LVTTL 12 V Internal 50 termination pin for D. TD 13 V Positive Supply Voltage. CC 14 V Positive Supply Voltage. CC 15 V Positive Supply Voltage. CC 16 V Positive Supply Voltage. CC EP Exposed pad. The exposed pad (EP) on the package bottom must be attached to a heatsinking conduit. The exposed pad may only be electrically connected to V . EE 1. In the differential configuration when the input termination pins (V , V ) are connected to a common termination voltage or left open, and TD TD if no signal is applied on D, D input, then the device will be susceptible to selfoscillation. www.onsemi.com 2