NB7L14M
2.5V/3.3VDifferential 1:4
Clock/Data Fanout Buffer/
Translator with CML
Outputs and Internal
NB7L14M
V Q0 Q0 V Exposed Pad (EP)
EE CC
16 15 14 13
V
1 12 Q1
TCLK
2 11
CLK
Q1
NB7L14M
CLK
3 10
Q2
V
4 9 Q2
TCLK
56 7 8
V Q3 Q3 V
EE CC
Figure 2. QFN16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 V Internal 50 Termination Pin for CLK.
TCLK
2 CLK LVPECL, CML, Inverted Differential Clock/Data Input. (Note 1)
LVCMOS, LVTTL,
LVDS
3 CLK LVPECL, CML, Noninverted Differential Clock/Data Input. (Note 1)
LVCMOS, LVTTL,
LVDS
4 V Internal 50 Termination Pin for CLK.
TCLK
5,16 V Power Supply Negative Supply Voltage. All V pins must be externally connected to a Power Supply to
EE EE
guarantee proper operation.
6 Q3 CML Output
Inverted Differential Output 3 with Internal 50 Source Termination Resistor. (Note 2)
7 Q3 CML Output Noninverted Differential Output 3 with Internal 50 Source Termination Resistor. (Note 2)
8,13 V Power Supply Positive Supply Voltage. All V pins must be externally connected to a Power Supply to
CC CC
guarantee proper operation.
9 Q2 CML Output Inverted Differential Output 2 with Internal 50 Source Termination Resistor. (Note 2)
10 Q2 CML Output
Noninverted Differential Output 2 with Internal 50 Source Termination Resistor. (Note 2)
11 Q1 CML Output Inverted Differential Output 1 with Internal 50 Source Termination Resistor. (Note 2)
12 Q1 CML Output Noninverted Differential Output 1 with Internal 50 Source Termination Resistor. (Note 2)
14 Q0 CML Output
Inverted Differential Output 0 with Internal 50 Source Termination Resistor. (Note 2)
15 Q0 CML Output Noninverted Differential Output 0 with Internal 50 Source Termination Resistor. (Note 2)
EP Exposed Pad. Thermal pad on the package bottom must be attached to a heatsinking
conduit to improve heat transfer. It is recommended to connect the EP to the lower
potential (V ).
EE
1. In the differential configuration when the input termination pins (V , V ) are connected to a common termination voltage or left open,
TCLK TCLK
and if no signal is applied on CLK and CLK, then the device will be susceptible to selfoscillation.
2. CML outputs require 50 receiver termination resistors to V for proper operation.
CC