NB7L32M 2.5V/3.3V, 14GHz 2 Clock Divider w/CML Output and Internal Termination Description NB7L32M V RV V Exposed Pad (EP) CC CC CC 16 15 14 13 VTCLK V 1 12 CC CLK 2 11 Q NB7L32M CLK Q 3 10 VTCLK V 4 9 CC 56 7 8 NC V V V EE EE EE Figure 1. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 VTCLK Internal 50 termination pin. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on CLK/CLK input then the device will be susceptible to self oscillation. 2 CLK ECL, CML, LVDS Input Noninverted differential input. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open and if no signal is applied on CLK/CLK input, then the device will be susceptible to self oscillation. 3 CLK ECL, CML, LVDS Input Inverted differential input. In the differential configuration when the input termin- ation pin (VTCLK, VTCLK) are connected to a common termination voltage or left open and if no signal is applied on CLK/CLK input, then the device will be susceptible to selfoscillation. 4 VTCLK Internal 50 termination pin. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open and if no signal is applied on CLK/CLK input, then the device will be susceptible to self oscillation. 5 NC No connect. NC pin must be left open. 6, 7, 8 V Negative supply voltage. EE 9, 12, 13, V Positive supply voltage. CC 14, 16 10 Q CML Output Inverted differential output. Typically terminated with 50 resistor to V . CC 11 Q CML Output Noninverted differential output. Typically terminated with 50 resistor to V . CC 15 R LVTTL/LVCMOS Reset Input. Internal pulldown to 75 k to V . EE EP Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a heatsinking conduit. EP is electrically isolated from V and V . CC EE