NB7V33M 1.8V / 2.5V, 10GHz 4 Clock Divider with CML Outputs MultiLevel Inputs w/ Internal Termination NB7V33M Exposed Table 1. TRUTH TABLE VCC R VCC VCC Pad (EP) CLK CLK R Q Q 16 15 14 13 x x H L H Z W L CLK 4 CLK 4 VTCLK 1 12 VCC Z = Low to High Transition 2 11 CLK Q W = High to Low Transition NB7V33M X = Dont Care CLK 3 10 Q VTCLK 4 9 VCC 56 7 8 VREFAC GND GND GND Figure 2. Pin Configuration (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description 1 VTCLK Internal 50 Termination Pin for CLK 2 CLK LVPECL, CML, Noninverted Differential CLK Input. Note 1. LVDS Input 3 CLK LVPECL, CML, Inverted Differential CLK Input. Note 1. LVDS Input 4 VTCLK Internal 50 Termination Pin for CLK 5 VREFAC Internally Generated Output Voltage Reference for Capacitor Coupled Inputs, Only 6 GND Negative Supply Voltage 7 GND Negative Supply Voltage 8 GND Negative Supply Voltage 9 VCC Positive Supply Voltage. Note 2. 10 Q CML Output Inverted Differential Output 11 Q CML Output NonInverted Differential Output 12 VCC Positive Supply Voltage. Note 2. 13 VCC Positive Supply Voltage. Note 2. 14 VCC Positive Supply Voltage. Note 2. 15 R LVCMOS Input Asynchronous Reset Input. Internal 75 k pulldown to GND. 16 VCC Positive Supply Voltage. Note 2. EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally con- nected to GND on the PC board. 1. In the differential configuration when the input termination pins (VTCLK/VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on CLK/CLK input, then the device will be susceptible to selfoscillation. Q/Q outputs have internal 50 source termination resistors. 2. All V and GND pins must be externally connected to a power supply for proper operation. CC