1.8 V/2.5 V CML 12.5 Gbps Programmable Pre-Emphasis Copper/Cable Driver with Selectable Equalizer Receiver MultiLevel Inputs w/ Internal Termination www.onsemi.com NB7VPQ16M Description 1 The NB7VPQ16M is a high performance single channel QFN16 MN SUFFIX programmable PreEmphasis CML Driver with a selectable Equalizer CASE 485G Receiver that operates up to 14 Gbps typical with a 1.8 V or 2.5 V power supply. When placed in series with a Data/Clock path, the MARKING DIAGRAM* 16 NB7VPQ16M inputs will compensate the degraded signal transmitted 1 across a FR4 PCB backplane or cable interconnect. Therefore, the NB7V serial data rate is increased by reducing InterSymbol Interference PQ16M (ISI) caused by losses in copper interconnect or long cables. ALYW The PreEmphasis buffer is controlled using a serial bus via the Serial Data In (SDIN) and Serial Clock In (SCLKIN) control inputs A = Assembly Location and contains circuitry which provides sixteen programmable L = Wafer Lot PreEmphasis settings to select the optimal output compensation Y = Year level. W = Work Week These selectable output levels will handle various backplane lengths = PbFree Package and cable lines. The first four SDIN bits (D3:D0) will digitally select (Note: Microdot may be in either location) 0 dB through 12 dB typical of deemphasis (see Table 1). *For additional marking information, refer to Application Note AND8002/D. For cascaded applications, the shifted SDIN and SCLKIN signals are presented at the SDOUT and SCLKOUT pins. SDOUT SDIN th SDI The 5 bit (LSB) of the serial data bits allows for enabling the SCLKIN SCLKOUT SLOAD equalization function of the receiver. IN The differential Data / Clock inputs incorporate a pair of internal DAC VT Q 50 termination resistors, in a 100 centertapped configuration, PE IN via the VT pin and will accept LVPECL, CML or LVDS logic levels. EQ Q This feature provides transmission line termination onchip, at the receiver end, eliminating external components. Figure 1. Simplified Logic Diagram The NB7VPQ16M is a member of the GigaComm Family of high performance Data/Clock products with PreEmphasis/Equalization ORDERING INFORMATION (PEEQ). See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. Features Maximum Input Data Rate > 12.5 Gbps Operating Range: V = 1.71 V to 2.625 V, GND = 0 V CC Maximum Input Clock Frequency > 8 GHz Internal Output Termination Resistors, 50 Drives Up To 18inches of FR4 QFN16 Package, 3 mm x 3 mm (16) Programmable Output Deemphasis Levels 0 dB 40C to +85C Ambient Operating Temperature through 12 dB These are PbFree Devices 200 ps Typical Propagation Delay Differential CML Outputs, 400 mV PeaktoPeak, Typical (PE = 0 dB) Semiconductor Components Industries, LLC, 2009 1 Publication Order Number: May, 2021 Rev. 1 NB7VPQ16M/DNB7VPQ16M (6) (15) SDIN SDOUT 5Bit Shift Register SCLKOUT(7) (14) SCLKIN EQEN D0 D1 D2 D3 V CCD V CC GND (13) SLOAD D/A Latch MultiLevel Inputs EQEN LVPECL, LVDS, CML (EQualizer ENable) 4Bit (2) IN DAC 50 0 (1) VT Q (11) 50 PreEmphasis 2:1 (3) IN Control Q (10) MUX EQ 1 CML Output Figure 2. Detailed Block Diagram of NB7VPQ16M Q Low Q High Q High Q Low Q High Q Low Q Low Q High Bit n Bit n+1 Bit n 1 Bit n+2 PE = 0dB PE = 12dB Q 20% 80% 0V V ODPE V OD0dB Q PE = 20log(V /V ) ODPE OD0dB t PE 130ps V Differential Output Voltage without Pre Emphasis OD0dB V Differential Output Voltage with Pre Emphasis ODPE Figure 3. Illustration of Output Waveform Definition www.onsemi.com 2