3.3 V/5 VProgrammable PLL Synthesized Clock Generator 50 MHz to 800 MHz NBC12439A www.onsemi.com Description The NBC12439A is a general purpose, PLL based synthesized clock source. The VCO will operate over a frequency range of 400 MHz to 800 MHz. The VCO frequency is sent to the N output divider, where 32 1 it can be configured to provide division ratios of 1, 2, 4 or 8. The VCO QFN32 and output frequency can be programmed using the parallel or serial MN SUFFIX interfaces to the configuration logic. Output frequency steps of CASE 488AM 16 MHz, 8 MHz, 4 MHz, or 2 MHz can be achieved using a 16 MHz crystal, depending on the output divider settings. The PLL loop filter MARKING DIAGRAM is fully integrated and does not require any external components. Features 1 NBC12 BestinClass Output Jitter Performance, 20 ps PeaktoPeak 439A 50 MHz to 800 MHz Programmable Differential PECL Outputs AWLYYW- W Fully Integrated PhaseLockLoop with Internal Loop Filter Parallel Interface for Programming Counter and Output Dividers During Powerup A = Assembly Location Minimal Frequency Overshoot WL = Wafer Lot YY = Year Serial 3Wire Programming Interface WW = Work Week Crystal Oscillator Inputs 10 MHz to 20 MHz = PbFree Package Operating Range: V = 3.135 V to 5.25 V CC (Note: Microdot may be in either location) CMOS and TTL Compatible Control Inputs Pin and Function Compatible with Motorola MC12439 and ORDERING INFORMATION MPC9239 Powerdown of PECL Outputs ( 16) Device Package Shipping QFN32 74 Units / Tube NBC12439AMNG 40C to 85C Ambient Operating Temperature (PbFree) These Devices are PbFree and are RoHS Compliant Semiconductor Components Industries, LLC, 2009 1 Publication Order Number: May, 2021 Rev. 15 NBC12439/DNBC12439A PWR DOWN +3.3 or 5.0 V PLL V CC F REF PHASE POWER 2 DETECTOR DOWN +3.3 or 5.0 V XTAL SEL VCO V FREF EXT CC FOUT 7BIT M N 2 XTAL1 COUNTER (1, 2, 4, 8) FOUT 400800 MHz 1020MHz OSC TEST XTAL2 LATCH LATCH OE S LOAD LATCH P LOAD 01 01 S DATA 2BIT SR 3BIT SR 7BIT SR S CLOCK 7 2 M 6:0 N 1:0 Figure 1. Block Diagram Table 1. OUTPUT DIVERSION Table 2. XTAL SEL AND OE N 1:0 Output Division Input 0 1 0 0 2 PWR DOWN F F 16 OUT OUT 0 1 4 XTAL SEL FREF EXT XTAL 1 0 8 OE* Outputs Disabled Outputs Enabled 1 1 1 *When disabled, FOUT goes LOW, FOUT goes HIGH. www.onsemi.com 2