NCD5700 High Current IGBT Gate Driver The NCD5700 is a highcurrent, highperformance standalone IGBT driver for high power applications that include solar inverters, motor control and uninterruptable power supplies. The device offers a www.onsemi.com costeffective solution by eliminating many external components. Device protection features include Active Miller Clamp, accurate UVLO, EN input, DESAT protection and Active Low FAULT output. MARKING The driver also features an accurate 5.0 V output and separate high and DIAGRAM low (VOH and VOL) driver outputs for system design convenience. The driver is designed to accommodate a wide voltage range of bias NCD5700DR2G SOIC16 supplies including unipolar and bipolar voltages. It is available in a AWLYWW D SUFFIX 16pin SOIC package. CASE 751B Features A = Assembly Location High Current Output (+4/6 A) at IGBT Miller Plateau Voltages WL = Wafer Lot Low Output Impedance of VOH & VOL for Enhanced IGBT Driving Y = Year WW = Work Week Short Propagation Delays with Accurate Matching G = PbFree Package Direct Interface to Digital Isolator/Optocoupler/Pulse Transformer for Isolated Drive, Logic Compatibility for Nonisolated Drive Active Miller Clamp to Prevent Spurious Gate Turnon PIN CONNECTIONS DESAT Protection with Programmable Delay Enable Input for Independent Driver Control 1 CLAMP EN 16 Tight UVLO Thresholds for Bias Flexibility VIN 2 15 VEEA Wide Bias Voltage Range including Negative VEE Capability VEE VREF 3 14 This Device is PbFree, HalogenFree and RoHS Compliant FLT 4 13 GND Typical Applications GNDA VOL 5 12 Solar Inverters NC VOH 6 11 Motor Control RSVD 10 VCC 7 Uninterruptible Power Supplies (UPS) DESAT NC 8 9 Rapid Shutdown for Photovoltaic Systems (Top View) VREF DESAT ORDERING INFORMATION VCC VCC See detailed ordering and shipping information on page 6 of EN this data sheet. VOH VOL CLAMP VIN GND VEE VEE FLT Figure 1. Simplified Application Schematic Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: June, 2017 Rev. 4 NCD5700/DNCD5700 SET TSD Q S CLR Q R VREF FLT I DESAT-CHG R DELAY EN-H + VDESAT-THR SET S Q - DESAT EN CLR R Q V CC VREF RIN-H V OH VIN VOL DELAY Bandgap VREF V VUVLO EE - + SET S Q V CC CLR R Q - + VMC-THR CLAMP GND VEE VEEA Figure 2. Detailed Block Diagram VREF EN CLAMP VREF CLAMP VIN VEEA VCC VREF LDO VEE FLT GND GNDA VOL NC VOH TSD RSVD VCC VCC UVLO NC DESAT DESAT Figure 3. Simplified Block Diagram www.onsemi.com 2 Logic Unit