LDO Regulator, 300 mA, Low Dropout Voltage, Ultra Low Noise, High PSRR with Power Good NCP164 www.onsemi.com The NCP164 is a 300 mA LDO, next generation of high PSRR, ultralow noise and low dropout regulators with Power Good open collector output. Designed to meet the requirements of RF and MARKING sensitive analog circuits, the NCP164 device provides ultralow noise, DIAGRAMS high PSRR and low quiescent current. The device also offer excellent 5 load/line transients. The NCP164 is designed to work with a 1 F input and a 1 F output ceramic capacitor. It is available in industry standard TSOP5 XXXAYW 5 CASE 483 TSOP5 and WDFN6 0.65P, 2 mm x 2 mm. 1 1 Features Operating Input Voltage Range: 1.6 V to 5.5 V WDFN6 2x2, 0.65P XXM CASE 511BR Available in Fixed Voltage Option: 1.2 V to 5 V Adjustable Version Reference Voltage: 1.1 V XXX = Specific Device Code 2% Accuracy Over Load and Temperature A = Assembly Location Ultra Low Quiescent Current Typ. 30 A L = Wafer Lot M = Month Code Standby Current: Typ. 0.1 A Y = Year Very Low Dropout: 110 mV at 300 mA for 3.3 V Variant W = Work Week Ultra High PSRR: Typ. 85 dB at 10 mA, f = 1 kHz = PbFree Package Ultra Low Noise: 9 V (Fixed Version) (Note: Microdot may be in either location) RMS Stable with a 1 F Small Case Size Ceramic Capacitors Available in TSOP5 3 mm x 1.5 mm x 1 mm CASE 483 PIN CONNECTONS WDFN6 2 mm x 2 mm x 0.75 mm CASE 511BR These Devices are PbFree, Halogen Free/BFR Free and are RoHS OUT 1 6 IN Compliant 2 5 ADJ/SNS GND GND Typical Applications 3 4 PG EN Communication Systems WDFN6 2x2 mm InVehicle Networking (Top View) Telematics, Infotainment and Clusters General Purpose Automotive ORDERING INFORMATION V See detailed ordering and shipping information on page 8 of IN IN this data sheet. OUT NCP164 C C OUT IN 1 F 1 F PG EN GND Ceramic Ceramic ON OFF Figure 1. Typical Application Schematic Semiconductor Components Industries, LLC, 2020 1 Publication Order Number: January, 2021 Rev. 1 NCP164/DNCP164 Table 1. PIN FUNCTION DESCRIPTION Pin No. Pin No. Pin TSOP5 WDFN6 Name Description 1 6 IN Input voltage supply pin 5 1 OUT Regulated output voltage. The output should be bypassed with small 1 F ceramic capacitor 3 4 EN Chip enable: Applying V < 0.2 V disables the regulator, Pulling V > 0.7 V enables the LDO EN EN 4 / 3 PG Power Good, open collector. Use 10 k to 100 k pullup resistor connected to output or input voltage 2 5 GND Common ground connection / 4 2 ADJ Adjustable output feedback pin (for adjustable version only) 2 SNS Sense feedback pin. Must be connected to OUT pin on PCB (for fixed versions only) N/C Not connected, pin can be tied to ground plane for better power dissipation EPAD EPAD Expose pad should be tied to ground plane for better power dissipation Table 2. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage (Note 1) V 0.3 to 6 V IN Output Voltage V 0.3 to V +0.3, max. 6 V OUT IN Chip Enable Input V 0.3 to 6 V CE Power Good Voltage V 0.3 to 6 V PG Power Good Current I 30 mA PG Output Short Circuit Duration t unlimited s SC Maximum Junction Temperature T 150 C J Storage Temperature T 55 to 150 C STG ESD Capability, Human Body Model (Note 2) ESD 2000 V HBM ESD Capability, Charged Device Model (Note 2) ESD 1000 V CDM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AECQ100002 (EIA/JESD22A114) ESD Charged Device Model tested per EIA/JESD22C101, Field Induced Charge Model www.onsemi.com 2