NCP4688DMU18TCG ON Semiconductor

NCP4688 Voltage Regulator - Low Noise, LDO Linear 150 mA The NCP4688 is a CMOS 150 mA LDO linear voltage regulator NCP4688 NCP4688xxxx NCP4688D Vin Vout Vin Vout Vref Vref Noise Reduction Noise Reduction CE CE Current Limit Current Limit GND GND Figure 2. Simplified Schematic Block Diagram Table 1. PIN FUNCTION DESCRIPTION Pin No. Pin No. SOT235 DFN 1x1 Pin Name Description 1 4 VIN Input pin 2 2 GND Ground pin 3 3 CE Chip enable pin (H active) 4 NC Non connected 5 1 VOUT Output pin *EP EP Exposed Pad (leave floating or connect to GND) Table 2. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage V 0 6 V V IN Output Voltage V 0.3 to V + 0.3 V OUT IN Chip Enable Input V 0 6 V V CE Power Dissipation SOT235 P 420 mW D Power Dissipation DFN 1.0 x 1.0 mm 400 Junction Temperature T 40 to 150 C J Storage Temperature T 55 to 125 C STG ESD Capability, Human Body Model (Note 1) ESD 2000 V HBM ESD Capability, Machine Model (Note 1) ESD 200 V MM Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AECQ100002 (EIA/JESD22A114) ESD Machine Model tested per AECQ100003 (EIA/JESD22A115) Latchup Current Maximum Rating tested per JEDEC standard: JESD78