NCP51198, NCV51198
1.5A DDR Memory
Termination Regulator
The NCP/NCV51198 is a simple, costeffective, highspeed linear
regulator designed to generate the V termination voltage rail for
TT
DDRI, DDRII and DDRIII memory. The regulator is capable of
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actively sourcing or sinking up to 1.5 A for DDRI, or up to 0.5 A
for DDRII /III while regulating the output voltage to within
MARKING
30 mV.
DIAGRAM
The output termination voltage is tightly regulated to track V =
TT
(V / 2) over the entire current range.
DDQ
The NCP/NCV51198 incorporates a highspeed differential
SOIC8NB EP
XXXXXX
8
amplifier to provide ultrafast response to line and load transients. PD SUFFIX
AYWW
CASE 751BU
Other features include extremely low initial offset voltage, excellent 1
load regulation, source/sink softstart and onchip thermal shutdown
protection.
The NCP/NCV51198 features the powersaving Suspend To Ram
XXXXXX = Specific Device Code
(STR) function which will tristate the regulator output and lower the A = Assembly Location
Y = Year
quiescent current drawn when the /SS pin is pulled low.
WW = Work Week
The NCP/NCV51198 is available in a SOIC8 Exposed Pad
= PbFree Package
package.
Features
PIN CONNECTION
Generate DDR Memory Termination Voltage (V )
TT
18
GND V
TT
For DDRI, DDRII, DDRIII Source / Sink Currents
/SS
PV
CC
Supports DDRI to 1.5 A, DDRII to 0.5 A (peak)
V
V
TTS
CC
Integrated Power MOSFETs with Thermal Protection
V V
REF DDQ
Stable with 10 F Ceramic V Capacitor
TT
SOIC8 EP
High Accuracy Output Voltage at FullLoad
Minimal External Component Count
ORDERING INFORMATION
Shutdown for Standby or Suspend to RAM (STR) mode
See detailed ordering, marking and shipping information in the
Builtin Soft Start
package dimensions section on page 8 of this data sheet.
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
These are PbFree Devices
Appications
Desktop PCs, Notebooks, and Workstations
Graphics Card DDR Memory Termination
Set Top Boxes, Digital TVs, Printers
Embedded Systems
Active Bus Termination
Semiconductor Components Industries, LLC, 2015
1 Publication Order Number:
April, 2015 Rev. 3 NCP51198/DNCP51198, NCV51198
1.5 A, DDRI /II /III TERMINATION REGULATOR
Figure 1. Typical Application Schematic
PIN FUNCTION DESCRIPTION NCP51198
Pin Number
SO8EP
Pin Name Pin Function
1 GND Common Ground.
2 /SS Suspend Shutdown supports Suspend To RAM function. CMOS compatible input sets V output to
TT
high impedance state. Logic HI = Enable, Logic LO = Shutdown.
3 V V is the V sense input.
TTS TTS TT
4 V V is an output pin that provides the buffered output of the internal reference voltage equal to half of
REF REF
V . Two resistors dividing down the V voltage on the pin to create the regulated output voltage.
DDQ DDQ
5 V The V pin is an input pin for creating the internal reference voltage to regulate V . The V volt-
DDQ DDQ TT DDQ
age is connected to an internal resistor divider. The central tap of resistor divider (V /2) is con-
DDQ
nected to the internal voltage buffer, which output is connected to V pin and the noninverting input
REF
of the error amplifier as the reference voltage.
6 V Power for the analog control circuitry.
CC
7 PV The PV pin provides the rail voltage from where the V pin draws load current. There is a limitation
CC CC TT
between V and PV . The PV voltage must be less or equal to the V voltage to ensure the
CC CC CC CC
correct output voltage regulation. The V source current capability is dependent on PV voltage. The
TT CC
higher the voltage on PV , the higher the source current.
CC
8 V Regulator output voltage capable of sinking and sourcing current while regulating the output rail.
TT
THERMAL Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple
PAD vias for maximum power dissipation performance.
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