NLSF1174 Hex D FlipFlop with Common Clock and Reset This device consists of six D flipflops with common Clock and Reset inputs. Each flipflop is loaded with a lowtohigh transition of the Clock input. Reset is asynchronous and active low. All NLSF1174 Q0 D0 D1 Q1 DATA D2 Q2 NONINVERTING INPUTS D3 OUTPUTS Q3 D4 Q4 D5 Q5 CLOCK RESET Figure 2. LOGIC DIAGRAM DESIGN/VALUE TABLE Design Criteria Value Unit Internal Gate Count* 40.5 ea Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0 W Speed Power Product .0075 pJ *Equivalent to a twoinput NAND gate. MAXIMUM RATINGS Parameter Symbol Value Unit DC Supply Voltage (Referenced to GND) V 0.5 to 7.0 V CC DC Input Voltage (Referenced to GND) V 1.5 to V 1.5 V IN CC DC Output Voltage (Referenced to GND) (Note 1) V 0.5 to V 0.5 V OUT CC DC Input Current, per Pin I 20 mA IN DC Output Current, per Pin I 25 mA OUT DC Supply Current, V and GND Pins I 50 mA CC CC Storage Temperature Range T 65 to 150 C STG Lead Temperature, 1 mm from Case for 10 Seconds PDIP, SOIC, TSSOP T 260 C L Junction Temperature Under Bias T 150 C J Thermal Resistance QFN 80 C/W JA Power Dissipation in Still Air at 85C QFN P 800 mW D Moisture Sensitivity MSL Level 1 Flammability Rating Oxygen Index: 30 to 35 F UL 94 V0 0.125 in R ESD Withstand Voltage Human Body Model (Note 2) V 2000 V ESD Machine Model (Note 3) 100 Charged Device Model (Note 4) 500 Latchup Performance Above V and Below GND at 85C (Note 5) I 300 mA CC LATCHUP Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. I absolute maximum rating must be observed. O 2. Tested to EIA/JESD22A114A. 3. Tested to EIA/JESD22A115A. 4. Tested to JESD22C101A. 5. Tested to EIA/JESD78. 6. For high frequency or heavy load considerations, see the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).