P3PS850BHG-08CR

P3PS850BH Timing-Safe Peak EMI Reduction IC Functional Description P3PS850BH is a versatile, TimingSafe peak EMI reduction IC. P3PS850BH accepts one input from an external reference, and locks P3PS850BH V DD MR SSEXTR CLKIN PLL ModOUT (Timing Safe) FS PD#/OE GND Figure 1. Block Diagram Table 1. PIN DESCRIPTION Pin# Pin Name Type Description 1 CLKIN I External reference Clock input. 2 PD# / OE I Power Down. Pull LOW to enable Power Down. Outputs will be tri stated when power down is en- abled. Pull HIGH to disable power down and enable output. NO default state. 3 FS I Frequency Select .NO default state. Refer to the Frequency Selection table 4 GND P Ground 5 ModOUT O Buffered modulated TimingSafe clock output 6 MR I Modulation Rate Select. When LOW, selects Low Modulation Rate. Selects High Modulation Rate when pulled HIGH. Has an internal pullup resistor. 7 SSEXTR I Analog Deviation Selection through external resistor to GND. 8 V P Supply Voltage DD Table 2. FREQUENCY SELECTION TABLE FS Frequency (MHz) 0 18 36 1 36 72 Table 3. OPERATING CONDITIONS Symbol Parameter Min Max Unit V Supply Voltage 2.3 3.6 V DD T Operating Temperature 20 +85 C A C Load Capacitance 15 pF L C Input Capacitance 7 pF IN