EK45450-02

Product Specification PE45450 UltraCMOS Power Limiter 9 kHz6 GHz Product Description Features The PE45450 is a HaRP technology-enhanced power limiter designed for use in high performance power Monolithic drop-in solution with no limiting applications in test and measurement equipment, external bias components reducing radar, military electronic counter measure receivers and design complexity wireless infrastructure transceivers and antennas. Adjustable power limiting threshold from +25 dBm to +35 dBm Unlike traditional PIN diode solutions, the PE45450 Max power handling achieves an adjustable input 1 dB compression point or +40 dBm CW (10W) limiting threshold via a low current control voltage (V ), CTRL +47 dBm Pulsed (50W) eliminating the need for external bias components, such Superior ESD rating and ESD protection as DC blocking capacitors, RF choke inductors, and bias 8 kV HBM on all pins resistors. 1 kV CDM on all pins 600V MM on all pins It delivers low insertion loss and high linearity under non- limiting input power levels and extremely fast response Unbiased power limiting operation and recovery time in a limiting event. It also offers Fast response and recovery time of 1 ns superior ESD rating and ESD protection for subsequent Dual mode operation circuitry. Power limiting mode Power reflecting mode The PE45450 is manufactured on Peregrines UltraCMOS process, a patented variation of silicon-on- insulator (SOI) technology on a sapphire substrate. Figure 2. Package Type Peregrines HaRP technology enhancements deliver 12-lead 3x3 mm QFN high linearity and excellent harmonics performance. It is an innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Diagram P OUT P1dB RF1 RF2 P IN Voltage Control and ESD V DOC-62357 CTRL Document No. DOC-44314-5 www.psemi.com 2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 12 PE45450 Product Specification Table 1. Electrical Specifications +25C (Z = Z = 50 ), unless otherwise noted S L Parameter Condition Min Typ Max Unit Operating frequency 9 kHz 6 GHz As shown Power limiting mode 9 kHz3 GHz 0.45 0.70 dB 1 Insertion loss 36 GHz 0.80 1.05 dB 9 kHz3 GHz 13 dB 1 Return loss 36 GHz 17 dB V = 2.5V 915 MHz 35 dBm CTRL P1dB / limiting threshold V = 1.5V 915 MHz 32 dBm CTRL V = 0.5V 915 MHz 25 dBm CTRL V = 2.5V 915 MHz 33.5 35.5 dBm CTRL 2 Leakage power V = 1.5V 915 MHz 33 35 dBm CTRL V = 0.5V 915 MHz 31.5 33.5 dBm CTRL Leakage power slope V = 1.0V 915 MHz 0.4 dB/dB CTRL 2 Unbiased leakage power V = 0V 915 MHz 25 27 dBm CTRL V = 2.5V 915 MHz 115 dBm CTRL Input IP2 V = 2.5V 6 GHz 110 dBm CTRL V = 2.5V 915 MHz 70 dBm CTRL Input IP3 V = 2.5V 6 GHz 60 dBm CTRL Response / recovery time 1 GHz 1 ns 3 Power reflecting mode 2 Leakage power V = +2.5V 915 MHz 2 8 dBm CTRL 4 Switching time State change to 10% RF 400 s Notes: 1. External matching is required to achieve the performance. 2. Measured with +40 dBm CW applied at input. 3. This mode requires the control voltage to toggle between +2.5V and 2.5V. At +2.5V, the limiter equivalent circuit is a low impedance to ground, reflecting most of the incident power back to the source. 4. State change is V toggle from 2.5V to +2.5V. CTRL 2013-2014 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-44314-5 UltraCMOS RFIC Solutions Page 2 of 12