DATASHEET 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE ICS1894-40 Description Features The ICS1894-40 is a low-power, physical-layer device Supports category 5 cables and above with attenuation in (PHY) that supports the ISO/IEC 10Base-T and excess of 24dB at 100 MHz. 100Base-TX Carrier-Sense Multiple Access/Collision Single-chip, fully integrated PHY provides PCS, PMA, Detection (CSMA/CD) Ethernet standards, ISO/IEC PMD, and AUTONEG sub layers functions of IEEE 8802.3. It is intended for RMII/MII, Node/Repeater standard. applications and includes the Auto-MDIX feature that 10Base-T and 100Base-TX IEEE 8802.3 compliant automatically corrects crossover errors in plant wiring. MIIM (MDC/MDIO) management bus for PHY register The ICS1894-40 incorporates Digital-Signal Processing configuration (DSP) control in its Physical-Medium Dependent (PMD) RMII interface support with external 50 MHz system clock sub-layer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with Single 3.3V power supply attenuation in excess of 24 dB at 100MHz. Highly configurable, supports: The ICS1894-40 provides a Serial-Management Interface Media Independent Interface (MII) for exchanging command and status information with a Auto-Negotiation with Parallel detection Station-Management (STA) entity. The ICS1894-40 Media-Dependent Interface (MDI) can be configured to Node applications, managed or unmanaged provide either half-duplex or full-duplex operation at data 10M or 100M full and half-duplex modes rates of 10 Mb/s or 100Mb/s. Loopback mode for Diagnostic Functions In addition, the ICS1894-40 includes a programmable LED Auto-MDI/MDIX crossover correction and interrupt output function. The LED outputs can be configured through registers to indicate the occurance of Low-power CMOS (typically 300 mW) certain events such as LINK, COLLISION, ACTIVITY, etc. Power-Down mode (typically 21mW) The purpose of the programmable interrupt output is to Clock and crystal supported in MII mode notify the PHY controller device immediately when a certain event happens instead of having the PHY controller Programmable LEDs continuously poll the PHY. The events that could be used to Interrupt output pin generate interrupts are: receiver error, Jabber, page Fully integrated, DSP-based PMD includes: received, parallel detect fault, link partner acknowledge, link status change, auto-negotiation complete, remote fault, Adaptive equalization and baseline-wander collision, etc. correction The ICS1894-40 has deep power modes that can result in Transmit wave shaping and stream cipher significant power savings when the link is broken. scrambler MLT-3 encoder and NRZ/NRZI encoder Applications: NIC cards, PC motherboards, switches, routers, DSL and cable modems, game machines, printers, Core power supply (3.3 V) network connected appliances, and industrial equipment. 3.3 V/1.8 V VDDIO operation supported Smart power control with deep power down feature Available in 40-pin (6mm x 6mm) QFN package, Pb-free Industrial Temp and Lead Free Not recommended for new designs For full/half duplex RMII only interface support, please refer to ICS1894-43 datasheet. For full/half duplex MII only interface support, please refer to ICS1894-44 datasheet. ICS1894-43 and ICS1894-44 are pin-compatible with ICS1894-40. IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 1 ICS1894-40 REV K 022412ICS1894-40 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER Block Diagram 100Base-T PCS PMA TP PMD Framer Clock Recovery MLT-3 10/100 MII/RMII Twisted- Interface Integrated CRS/COL Link Monitor Stream Cipher MAC Detection Signal Detection Adaptive Equalizer Pair MUX Switch Interface Parallel to Serial Error Detection Baseline Wander Interface to 4B/5B Correction Magnetics Modules and 10Base-T RJ45 Connector MII Low-Jitter Smart Power Auto- Configuration Extended MII Clock Control Negotiation and Status Register Management Synthesizer Block Set Interface Clock Power LEDs and PHY Address Pin Assignment 31 31 AMDIX 1 TXD0 AMDIX 1 TXD0 TXEN TP AP TXEN TP AP TP AN SPEED/TXCLK TP AN SPEED/TXCLK VSS NOD/RXER VSS NOD/RXER VDD NLG40 Without Ground Connecting to ANSEL/RXCLK VDD ANSEL/RXCLK NLG40 Without Ground Connecting to Thermal Pad TXER TP BN Thermal Pad TXER TP BN SPEED TP BP SPEED TP BP RMII/RXDV VDD RMII/RXDV VDD FDPX/RXD0 TCSR FDPX/RXD0 TCSR 21 SI/LED4 VSS 11 21 SI/LED4 VSS 11 40-pin MLF 40-pin MLF IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 2 ICS1894-40 REV K 022412 RESET N P1/ISO/LED1 P1/LED1 RESET N P2/INT P0/LED0 P2/INT P0/LED0 MDIO P4/LED2 P4/LED2 MDIO REFIN MDC REFIN MDC VDDIO REFOUT VDDIO REFOUT HWSW/CRS TXD3 TXD3 HWSW/CRS TXD2 REGPIN/COL TXD2 REGPIN/COL TXD1 AMDIXRXD3 TXD1 AMDIXRXD3 P3/RXD2 LED3 P3/RXD2 LED3 RXTR1RXD1 VDDD RXTR1RXD1 VDDD