1.8V to 3.3V, High-Performance 1:4 Clock Buffer 2304NZL DATASHEET Description Features The 2304NZL is a high-performance, low skew, low jitter 1:4 Low input to output propagation delay (1.8ns, 3.3V) LVCMOS clock buffer. The 2304NZL is ideal for PCI/PCI-X or Low output skew: 40ps max networking applications. Glitch-free Output Enable Function The 2304NZL supports a synchronous glitch-free Output 1.8V to 3.3V power supply Enable function to eliminate any potential intermediate Packaged in small 8-pin 2mm x 2mm DFN package, as well incorrect output clock cycles when enabling or disabling as standard TSSOP and SOIC packages outputs. Industrial temperature range (-40C to +85C) Block Diagram Logic OE Control CLK IN CLK0 CLK1 CLK2 CLK3 2304NZL JANUARY 31, 2017 1 2017 Integrated Device Technology, Inc.2304NZL DATASHEET Pin Assignment CLK IN 1 8 CLK3 CLK3 1 8 CLK IN OE 2 7 OE CLK2 CLK2 2 7 CLK0 3 6 VDD CLK0 VDD 3 6 GND 4 5 CLK1 GND CLK1 4 5 8-pin DFN 8-pin TSSOP/SOIC Functionality Table Inputs Outputs CLK IN OE CLK(3:0) 00 Low 01 0 10 Low 11 1 Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 CLK IN Input Clock input. 2 OE Input Output Enable for the clock outputs. Outputs are enabled when forced HIGH. Outputs are forced to logic LOW when OE is forced LOW. 3 CLK0 Output Clock output 0. 4 GND Power Power supply ground. 5 CLK1 Output Clock output 1. 6 VDD Power Connect +1.8V, +2.5V or +3.3V power supply. 7 CLK2 Output Clock output 2. 8 CLK3 Output Clock output 3. External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 F should be connected between VDD on pin 6 and GND on pin 4, as close to the device as possible. A termination resistor should be used on each clock output if the trace is longer than 1 inch. See the Test Loads section for recommended values. To achieve the low output skew that the 2304NZL is capable of, careful attention must be paid to board layout. Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will be degraded. 1.8V TO 3.3V, HIGH-PERFORMANCE 1:4 CLOCK BUFFER 2 JANUARY 31, 2017