DATA SH EET DATASHEET 3.3 VOLT ZERO DELAY CLOCK MULTIPLIER 2 3 0 8 B Description Features The 2308B is a high-speed phase-lock loop (PLL) clock Phase-Lock Loop Clock Distribution for Applications multiplier. It is designed to address high-speed clock ranging from 10MHz to 133MHz operating frequency distribution and multiplication applications. The zero delay Distributes one clock input to two banks of four outputs is achieved by aligning the phase between the incoming Separate output enable for each output bank clock and the output clock, operable within the range of 10 to 133MHz. External feedback (FBK) pin is used to synchronize the outputs to the clock input The 2308B has two banks of four outputs each that are Output Skew < 200 ps controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In Low jitter < 200 ps cycle-to-cycle test mode, the PLL is turned off, and the input clock directly 1x, 2x, 4x output options (see Available Options for drives the outputs for system testing purposes. In the 2308B table) absence of an input clock, the 2308B enters power down, No external RC network required and the outputs are tri-stated. In this mode, the device will draw less than 25A. Operates at 3.3 V V DD The 2308B is available in six unique configurations for both Available in 16-SOIC and 16-TSSOP packages prescaling and multiplication of the Input REF Clock. (see Available in commercial and industrial temperature Available Options for 2308B table.) ranges The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. Block Diagram 2021 Renesas Electronics Corporation 1 R31DS0037EU0300 MAY 21, 20212308B 3.3 VOLT ZERO DELAY CLOCK MULTIPLIER CLOCK MULTIPLIER Pin Assignment Applications SDRAM Telecom Datacom PC Motherboards/Workstations Critical Path Delay Designs 1 Function Table Select Input Decoding S2 S1 CLKA CLKB Output PLL Shut Source Down L L Tri-state Tri-state PLL Y L H Driven Tri-state PLL N H L Driven Driven REF Y H H Driven Driven PLL N Note 1: H = HIGH voltage level L = LOW voltage level Pin Descriptions Pin Number Pin Name Pin Description 1 1 REF Input Reference Clock, 5 Volt Tolerant Input. 2 2 CLKA1 Clock Output for Bank A. 2 3 CLKA2 Clock Output for Bank A. 4 VDD 3.3 V Supply. 5 GND Ground. 2 6 CLKB1 Clock Output for Bank B. 2 7 CLKB2 Clock Output for Bank B. 3 8 S2 Select Input, Bit 2. 3 9 S1 Select Input, Bit 1. 2 10 CLKB3 Clock Output for Bank B. 2 11 CLKB4 Clock Output for Bank B. 12 GND Ground. 13 VDD 3.3 V Supply. 2 14 CLKA3 Clock Output for Bank A. 2 15 CLKA4 Clock Output for Bank A. 16 FBK PLL Feedback Input. Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-up on these inputs. 2021 Renesas Electronics Corporation 2 R31DS0037EU0300 MAY 21, 2021