5T30553DCGI Renesas

DATASHEET LOW SKEW 1 TO 4 CLOCK BUFFER IDT5T30553 Description Features The IDT5T30553 is a low skew, single input to four output, Extremely low skew outputs (50 ps maximum) clock buffer. Packaged in 8-pin SOIC Pb-free, RoHS compliant IDT makes many non-PLL and PLL based low skew output Low power CMOS technology devices as well as Zero Delay Buffers to synchronize Operating voltages of 2.5 V to 3.3 V clocks. Contact us for all of your clocking needs. Output Enable pin tri-states outputs Commercial (0 to +70C) and Industrial (-40C to +85C) temperature ranges Block Diagram Q0 Q1 ICLK Q2 Q3 Output Enable IDT LOW SKEW 1 TO 4 CLOCK BUFFER 1 IDT5T30553 REV F 121013IDT5T30553 LOW SKEW 1 TO 4 CLOCK BUFFER FAN OUT BUFFER Pin Assignment VDD 1 8 OE Q0 2 7 Q3 Q1 3 6 Q2 GND 4 5 ICLK 8-pin SOIC Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 VDD Power Connect to +2.5 V or +3.3 V. 2 Q0 Output Clock output 0. 3 Q1 Output Clock output 1. 4 GND Power Connect to ground. 5 ICLK Input Clock input. 6 Q2 Output Clock Output 2. 7 Q3 Output Clock Output 3. 8 OE Input Output Enable. Tri-states outputs when low. Connect to VDD for normal operation. External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 F should be connected between VDD on pin 1 and GND on pin 4, as close to the device as possible. A 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. To achieve the low output skew that the IDT5T30553 is capable of, careful attention must be paid to board layout. Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least 15 ps of skew. IDT LOW SKEW 1 TO 4 CLOCK BUFFER 2 IDT5T30553 REV F 121013