2.5V LVDS 1:6 Clock Buffer IDT5T9306 Terabuffer II DATA SHEET FEATURES: DESCRIPTION: Guaranteed Low Skew < 40ps (max) The IDT5T9306 2.5V differential clock buffer is a user-selectable Very low duty cycle distortion < 125ps (max) differential input to six LVDS outputs. The fanout from a differential input High speed propagation delay < 1.75ns (max) to six LVDS outputs reduces loading on the preceding driver and provides Additive phase jitter, RMS 0.159ps (typical) 125MHz an efficient clock distribution network. The IDT5T9306 can act as a Up to 1GHz operation translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL Selectable inputs (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V Hot insertable and over-voltage tolerant inputs LVTTL input can also be used to translate to LVDS outputs. The redundant 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL input capability allows for an asynchronous change-over from a primary (3.3V), CML, or LVDS input interface clock source to a secondary clock source. Selectable reference inputs are Selectable differential inputs to six LVDS outputs controlled by SEL. Power-down mode The IDT5T9306 outputs can be asynchronously enabled/disabled. When 2.5V VDD disabled, the outputs will drive to the value selected by the GL pin. Multiple Available in VFQFPN package power and grounds reduce noise. APPLICATIONS: Clock distribution FUNCTIONAL BLOCK DIAGRAM GL G Q1 OUTPUT CONTROL Q1 PD Q2 OUTPUT CONTROL Q2 A1 1 A1 Q3 OUTPUT CONTROL Q3 A2 Q4 OUTPUT 0 CONTROL A2 Q4 Q5 OUTPUT SEL CONTROL Q5 Q6 OUTPUT CONTROL Q6 IDT5T9306 REVISION C NOVEMBER 29, 2012 1IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER II PIN CONFIGURATION 28 27 26 25 24 23 22 21 G 1 PD 20 VDD VDD 2 Q4 19 Q1 3 Q4 GND 18 Q1 4 VDD 5 17 VDD A1 6 16 A2 A1 7 15 A2 14 8910 11 12 13 VFQFPN TOP VIEW IDT5T9306 REVISION C NOVEMBER 29, 2012 2 SEL GL VDD VDD Q2 Q6 Q2 Q6 Q3 Q5 Q3 Q5 VDD NC