70V3379S HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: Data input, address, byte enable and control registers True Dual-Port memory cells which allow simultaneous Self-timed write allows fast cycle time access of the same memory location Separate byte controls for multiplexed bus and bus High-speed clock to data access matching compatibility Commercial: 4.2/5/6ns (max.) LVTTL- compatible, single 3.3V (150mV) power supply for Industrial: 5ns (max) core Pipelined output mode LVTTL- compatible, selectable 3.3V (150mV)/2.5V (125mV) Counter enable and reset features power supply for I/Os and control signals on each port Dual chip enables allow for depth expansion without Industrial temperature range (-40C to +85C) is additional logic available for selected speeds Full synchronous operation on both ports Available in a 128-pin Thin Quad Plastic Flatpack (TQFP) 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth) and 208-pin fine pitch Ball Grid Array, and 256-pin Fast 4.2ns clock to data out Ball Grid Array 1.8ns setup to clock and 0.7ns hold on all control, data, and Green parts available, see ordering information address inputs 133MHz Functional Block Diagram UBL UBR LBR LBL R/WL R/WR B B B B W W W W 0 1 1 0 CE0L CE0R L L R R CE1L CE1R OEL OER Dout0-8 L Dout0-8 R Dout9-17 L Dout9-17 R 32K x 18 MEMORY ARRAY , . I/O0L - I/O17 L Din L Din R I/O0R-I/O17R CLKL CLKR A14L A14R Counter/ Counter/ A0L A 0R Address ADDR L ADDR R Address CNTRSTL CNTRSTR Reg. ADSR Reg. ADSL CNTENL CNTENR 4833 tbl 01 JULY 2019 1 DSC 4833/15 2019 Integrated Device Technology, Inc.70V3379S High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70V3379 is a high-speed32K x 18 bit synchronous Dual-Port in bursts. An automatic power down feature, controlled by CE0 and CE1, RAM. The memory array utilizes Dual-Port memory cells to allow permits the on-chip circuitry of each port to enter a very low standby power simultaneous access of any address from both ports. Registers on control, mode. data, and address inputs provide minimal setup and hold times. The timing The 70V3379 can support an operating voltage of either 3.3V or 2.5V latitude provided by this approach allows systems to be designed with very on one or both ports, controllable by the OPT pins. The power supply for short cycle times. With an input data register, the IDT70V3379 has been the core of the device (VDD) remains at 3.3V. optimized for applications having unidirectional or bidirectional data flow (1,2,3,4) Pin Configuration 1 2 3 4 5 6 7 8 9 11 12 13 14 10 15 16 17 NC NC A12L VSS A I/O9L VSS NC NC A8L NC VDD CLKL CNTEN L A4L A0L OPTL NC VSS A13L A9L CE0L VSS VDDQR I/O8L NC NC NC VSS NC NC ADSL A5L A1L VSS B VDDQL I/O9R VDDQR VDD NC A14L A10L UBL CE1L VSS R/WL A6L A2L VDD I/O8R NC VSS C NC VSS I/O10L NC NC A11L A7L LBL VDD OEL CNTRST L VDDQL I/O7L I/O7R A3L VDD NC D I/O 11L NC VDDQR I/O10R I/O6L NC VSS NC E I/O6R VDDQL I/O11R NC VSS VSS NC VDDQR F NC VSS I/O12L I/O5L NC NC VDDQL NC G 70V3379 NC VDDQR I/O12R VDD NC I/O5R VDD VSS H (5) BF208 VDDQL VDD VSS VSS VSS VDD VSS VDDQR J 208-Pin fpBGA (6) I/O4R I/O14R VSS I/O13R VSS I/O3R VDDQL VSS K Top View NC I/O14L VDDQR I/O13L NC I/O3L VSS I/O4L L VDDQL NC I/O15R VSS VSS NC I/O2R VDDQR M NC VSS NC I/O15L I/O1R VDDQL NC I/O2L N A8R I/O16R I/O16L VDDQR NC NC NC A12R NC VDD CLKR CNTEN R A4R NC I/O1L VSS NC P VSS NC I/O17R NC NC A13R A9R NC CE0R VSS ADSR A5R A1R VSS VDDQL I/O0R VDDQR R NC I/O17L VDDQL VSS A14R A10R UBR CE1R VSS A6R A2R VSS VSS NC NC R/WR NC T VSS NC VDD NC NC A11R A7R LBR VDD OER CNTRST R A3R A0R VDD OPTR NC I/O0L U 4833 drw 02 NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 6.422