Product Information

71124S12YG

71124S12YG electronic component of Renesas

Datasheet
IDT SRAM 128Kx8 ASYNCHRONOUS 5.0V STATIC RAM

Manufacturer: Renesas
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete
Availability Price Quantity
0 - WHS 1


Multiples : 152

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71124S12YG
Renesas

N/A

Obsolete
0 - WHS 2

MOQ : 1
Multiples : 1

Stock Image

71124S12YG
Renesas

1 : USD 8.532
10 : USD 3.078
115 : USD 2.6892
253 : USD 2.6028
506 : USD 2.592
1012 : USD 2.4084
2507 : USD 2.376
5014 : USD 2.3004
N/A

Obsolete
     
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RoHS - XON
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CMOS Static RAM 71124 1 Meg (128K x 8-Bit) Revolutionary Pinout Features Description 128K x 8 advanced high-speed CMOS static RAM The IDT71124 is a 1,048,576-bit high-speed static RAM organized as JEDEC revolutionary pinout (center power/GND) for 128K x 8. It is fabricated using high-performance, high-reliability CMOS reduced noise. technology. This state-of-the-art technology, combined with innovative Equal access and cycle times circuit design techniques, provides a cost-effective solution for high-speed Commercial: 12/15/20ns memory needs. The JEDEC centerpower/GND pinout reduces noise Industrial: 15/20ns generation and improves system performance. One Chip Select plus one Output Enable pin The IDT71124 has an output enable pin which operates as fast as 6ns, Bidirectional inputs and outputs directly TTL-compatible with address access times as fast as 12ns available. All bidirectional inputs Low power consumption via chip deselect and outputs of the IDT71124 are TTL-compatible and operation is from Available in a 32-pin 400 mil Plastic SOJ. a single 5V supply. Fully static asynchronous circuitry is used no clocks or refreshes are required for operation. The IDT71124 is packaged in a 32-pin 400 mil Plastic SOJ. Functional Block Diagram A0 1,048,576-BIT ADDRESS MEMORY ARRAY DECODER A16 8 8 I/O0-I/O7 I/O CONTROL , 8 WE CONTROL OE LOGIC CS 3514 drw 01 1 Feb.27.2071124 CMOS Static RAM 1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges Pin Configuration (1) Absolute Maximum Ratings Symbol Rating Value Unit A16 A0 1 32 (2) (2) VTERM Terminal Voltage with -0.5 to +7.0 V A1 2 31 A15 Respect to GND A2 3 30 A14 o TA Operating Temperature 0 to +70 C A3 4 29 A13 o CS 5 28 OE TBIAS Temperature -55 to +125 C 71124 Under Bias I/O0 6 27 I/O7 PBG32 I/O6 I/O1 7 26 o TSTG Storage -55 to +125 C VCC 8 25 GND Temperature VCC GND 9 24 PT Power Dissipation 1.25 W I/O2 , 10 23 I/O5 I/O4 IOUT DC Output Current 50 mA I/O3 11 22 WE 12 21 A12 3514 tbl 02 NOTES: A4 13 20 A11 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may A5 14 19 A10 cause permanent damage to the device. This is a stress rating only and functional A6 15 18 A9 operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum A7 16 17 A8 rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.5V. 3514 drw 02 SOJ Top View Capacitance (TA = +25C, f = 1.0MHz) (1) Symbol Parameter Conditions Max. Unit (1,2) Truth Table CIN Input Capacitance VIN = 3dV 8 pF CS OE WE I/O Function CI/O I/O Capacitance VOUT = 3dV 8 pF OUT Read Data LL H DATA 3514 tbl 03 NOTE: LX L DATAIN Write Data 1. This parameter is guaranteed by device characterization, but is not production tested. L H H High-Z Output Disabled H X X High-Z Deselected - Standby (ISB) (3) VHC X X High-Z Deselected - Standby (ISB1) Recommended Operating Temperature and Supply Voltage 3514 tbl 01 NOTES: 1. H = VIH, L = VIL, x = Don t care. Grade Temperature GND VCC 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC. Commercial 0C to +70C 0V 5.0V 10% Industrial 40C to +85C 0V 5.0V 10% 3514 tbl 04 Recommended DC Operating Conditions Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 VCC +0.5 V (1) VIL Input Low Voltage -0.5 0.8 V NOTE: 3514 tbl 05 1. VIL (min.) = 1.5V for pulse width less than 10ns, once per cycle. 6.42 2 Feb.27.20

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory
CEL (RENESAS)
ID4
IDT
IDT, Integrated Device Technology Inc
INTEGRATED DEVICE
INTEGRATED DEVICE TECHNOLOGY
INTEGRATED DEVICES TECH AID
Intersil
INTERSIL - FGC
Intersil(Renes as Electronics)
Intersil(Renesas Electronics)
ITS
REA
RENESAS
RENESAS (IDT)
RENESAS (INTERSIL)
Renesas / IDT
Renesas / Intersil
Renesas Electronics
Renesas Electronics America
RENESAS TECHNOLOGY

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