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723651L15PFG

723651L15PFG electronic component of Renesas
Part No.723651L15PFG
Manufacturer: Renesas
Category:FIFO
Description: FIFO 2KX36 SYNCFIFO
Datasheet: 723651L15PFG Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete
Availability Price Quantity
0 - WHS 1

MOQ : 90
Multiples : 90
90 : USD 98.0571
N/A

Obsolete
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CMOS SyncFIFO 512 x 36 IDT723631 1,024 x 36 IDT723641 2,048 x 36 IDT723651 Output Ready (OR) and Almost-Empty (AE) flags synchronized FEATURES: by CLKB Storage capacity: Available in space-saving 120-pin thin quad flat package (TQFP) IDT723631 - 512 x 36 Green parts available, see ordering information IDT723641 - 1,024 x 36 IDT723651 - 2,048 x 36 DESCRIPTION: Supports clock frequencies up to 67 MHz Fast access times of 11ns The IDT723631/723641/723651 is a monolithic high-speed, low-power, Free-running CLKA and CLKB can be asynchronous or coinci- CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz dent (permits simultaneous reading and writing of data on a and has read access times as fast as 11ns. The 512/1,024/2,048 x 36 single clock edge) dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory Clocked FIFO buffering data from Port A to Port B has retransmit capability, which allows previously read data to be ac- Synchronous read retransmit capability cessed again. The FIFO has flags to indicate empty and full conditions and Mailbox register in each direction two programmable flags (Almost-Full and Almost-Empty) to indicate when a Programmable Almost-Full and Almost-Empty flags selected number of words is stored in memory. Communication between Microprocessor interface control logic each port may take place with two 36-bit mailbox registers. Each mailbox Input Ready (IR) and Almost-Full (AF) flags synchronized by register has a flag to signal when new mail has been stored. Two or more CLKA FUNCTIONAL BLOCK DIAGRAM MBF1 Mail 1 Register CLKA Port-A CSA Control W/RA ENA Logic RAM ARRAY MBA 512 x 36 1,024 x 36 2,048 x 36 Reset RST Logic RTM 36 Read Write RFM Pointer Pointer A0 - A35 B0 - B35 Status Flag OR IR Logic AE AF FS0/SD Flag Offset FS1/SEN Registers 10 CLKB CSB Port-B W/RB Control ENB Logic Mail 2 MBB Register 3023 drw01 MBF2 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2014 1 2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2023/8 Input Register Output Sync Register Retransmit LogicIDT723631/723641/723651 CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL 512 x 36, 1,024 x 36 and 2,048 x 36 TEMPERATURE RANGES port are arranged to provide a simple interface between microprocessors DESCRIPTION (CONTINUED) and/or buses with synchronous control. devices may be used in parallel to create wider data paths. Expansion is The Input Ready (IR) flag and Almost-Full (AF) flag of the FIFO are also possible in word depth. two-stage synchronized to CLKA. The Output Ready (OR) flag and Al- These devices are a clocked FIFO, which means each port employs a most-Empty (AE) flag of the FIFO are two-stage synchronized to CLKB. synchronous interface. All data transfers through a port are gated to the Offset values for the Almost-Full and Almost-Empty flags of the FIFO can be LOW-to-HIGH transition of a continuous (free-running) port clock by en- programmed from port A or through a serial input. able signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each PIN CONFIGURATION A35 1 90 B35 A34 2 89 B34 A33 3 88 B33 A32 4 87 B32 VCC 5 86 GND A31 6 85 B31 A30 7 84 B30 GND 8 B29 83 A29 9 B28 82 A28 10 B27 81 A27 11 B26 80 A26 12 VCC 79 A25 13 B25 78 A24 14 B24 77 A23 15 GND 76 GND 16 B23 75 A22 17 B22 74 VCC 18 B21 73 A21 19 B20 72 A20 20 B19 71 A19 21 B18 70 A18 22 GND 69 GND 23 B17 68 A17 24 B16 67 A16 25 VCC 66 A15 26 B15 65 A14 27 B14 64 A13 28 B13 63 VCC 29 B12 62 A12 30 GND 61 3023 drw03 TQFP (PNG120, ORDER CODE: PF) TOP VIEW NOTE: 1. NC No Connection 2 31 GND GND 120 32 CLKA A11 119 33 ENA A10 118 34 W/RA A9 117 35 CSA A8 116 36 IR A7 115 37 OR A6 114 VCC 38 GND 113 AF 39 A5 112 40 AE A4 111 VCC 41 A3 110 MBF2 VCC 42 109 MBA 43 A2 108 44 RST A1 107 45 GND A0 106 46 GNDGND FS0/SD 105 47 FS1/SEN B0 104 48 RTM B1 103 49 RFM B2 102 50 VCC B3 101 51 NC B4 100 52 MBB B5 99 GND GND 53 98 54 MBF1 B6 97 VCC 55 GND 96 56 CSB B7 95 57 W/RB B8 94 58 ENB 93 B9 59 CLKB B10 92 60 VCC B11 91

Tariff Desc

8542.32.00 32 No ..CMOS and MOS Read Only Memory and Programmable Read Only Memory whether erasable or non-erasable (for example, flash memory, EPROM, E2PROM, EAPROM, NOVRAM, ROM and PROM)
CEL (RENESAS)
ID4
IDT
IDT, Integrated Device Technology Inc
INTEGRATED DEVICE
INTEGRATED DEVICE TECHNOLOGY
INTEGRATED DEVICES TECH AID
Intersil
INTERSIL - FGC
Intersil(Renes as Electronics)
Intersil(Renesas Electronics)
ITS
REA
RENESAS
RENESAS (IDT)
RENESAS (INTERSIL)
Renesas / IDT
Renesas / Intersil
Renesas Electronics
Renesas Electronics America
RENESAS TECHNOLOGY

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