CMOS DUAL SyncFIFO IDT72805LB DUAL 256 x 18 IDT72815LB DUAL 512 x 18 DUAL 1,024 x 18 IDT72825LB DUAL 4,096 x 18 IDT72845LB LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Easily expandable in depth and width FEATURES: Asynchronous or coincident Read and Write clocks The IDT72805LB is equivalent to two IDT72205LB 256 x 18 FIFOs Asynchronous or synchronous programmable Almost-Empty The IDT72815LB is equivalent to two IDT72215LB 512 x 18 FIFOs and Almost-Full flags with default settings The IDT72825LB is equivalent to two IDT72225LB 1,024 x 18 FIFOs Half-Full flag capability The IDT72845LB is equivalent to two IDT72245LB 4,096 x 18 FIFOs Output Enable puts output data bus in high-impedance state Offers optimal combination of large capacity (8K), high speed, High-performance submicron CMOS technology design flexibility, and small footprint Available in the 128-pin Thin Quad Flatpack (TQFP). Also Ideal for the following applications: available for the IDT72805LB/72815LB/72825LB, in the 121-lead, - Network switching 16 x 16 mm plastic Ball Grid Array (PBGA) - Two level prioritization of parallel data Industrial temperature range (40C to +85C) is available - Bidirectional data transfer Green parts available, see ordering information - Bus-matching between 18-bit and 36-bit data paths - Width expansion to 36-bit per package - Depth expansion to 8,192 words per package DESCRIPTION: 10ns read/write cycle time, 6.5ns access time The IDT72805LB/72815LB/72825LB/72845LB are dual 18-bit-wide syn- IDT Standard or First Word Fall Through timing chronous (clocked) First-in, First-out (FIFO) memories. One dual IDT72805LB/ Single or double register-buffered Empty and Full Flags FUNCTIONAL BLOCK DIAGRAM HFA/(WXOA) FFA/IR PAEA A EFA/ WCLKA ORA WCLKB DA0-DA17 DB0-DB17 WENA LDA WENB LDB PAFA INPUT OFFSET REGISTER REGISTER INPUT OFFSET REGISTER REGISTER FFB/IRB FLAG PAFB WRITE FLAG LOGIC WRITE CONTROL EFB/ORB RAM LOGIC CONTROL LOGIC PAEB ARRAY RAM LOGIC HFB/(WXOB) 256 x 18 ARRAY 512 x 18 256 x 18 READ 1,024 x 18 512 x 18 WRITE 4,096 x 18 POINTER 1,024 x 18 READ POINTER WRITE 4,096 x 18 POINTER POINTER READ FLA READ CONTROL WXIA EXPANSION CONTROL LOGIC (HFA)/WXOA LOGIC LOGIC EXPANSION OUTPUT RXIA LOGIC REGISTER OUTPUT RXOA REGISTER RESET LOGIC RSA RESET LOGIC RCLKB RSB RCLKA OEB QA0-QA17 RENB OEA RENA RXOB QB0-QB17 RXIB (HFB)/WXOB WXIB 3139 drw 01 FLB IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2018 1 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3139/10TM IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFO COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18 Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the program- DESCRIPTION (Continued) mable flags is controlled by a simple state machine, and is initiated by asserting 72815LB/72825LB/72845LB device is functionally equivalent to two the Load pin (LD). A Half-Full flag (HF) is available for each FIFO that is IDT72205LB/72215LB/72225LB/72245LB FIFOs in a single package with all implemented as a single device configuration. associated control, data, and flag lines assigned to independent pins. These There are two possible timing modes of operation with these devices: IDT devices are very high-speed, low-power First-In, First-Out (FIFO) memories Standard mode and First Word Fall Through (FWFT) mode. with clocked read and write controls. These FIFOs are applicable for a wide In IDT Standard Mode, the first word written to an empty FIFO will not variety of data buffering needs, such as optical disk controllers, Local Area Networks appear on the data output lines unless a specific read operation is performed. (LANs), and interprocessor communication. A read operation, which consists of activating REN and enabling a rising RCLK Each of the two FIFOs contained in these devices has an 18-bit input and edge, will shift the word from internal memory to the data output lines. output port. Each input port is controlled by a free-running clock (WCLK), and In FWFT mode, the first word written to an empty FIFO is clocked directly an input enable pin (WEN). Data is read into the synchronous FIFO on every to the data output lines after three transitions of the RCLK signal. A REN does clock when WEN is asserted. The output port of each FIFO bank is controlled not have to be asserted for accessing the first word. by another clock pin (RCLK) and another enable pin (REN). The Read Clock These devices are depth expandable using a daisy-chain technique or First can be tied to the Write Clock for single clock operation or the two clocks can Word Fall Through (FWFT) mode. The XI and XO pins are used to expand the run asynchronous of one another for dual-clock operation. An Output Enable FIFOs. In depth expansion configuration, FL is grounded on the first device and pin (OE) is provided on the read port of each FIFO for three-state control of the set to HIGH for all other devices in the Daisy Chain. output. The IDT72805LB/72815LB/72825LB/72845LB are fabricated using high- The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready speed submicron CMOS technology. (EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags, PIN CONFIGURATIONS PIN 1 A WCLKA DA3 DA1 DA0 DB13 DB16 RCLKB LDB RSB QB17 QB16 B PAFA DA4 WENA DA2 DB12 DB15 RENB OEB EFB QB15 QB14 C FFA RXIA WXIA DA5 DB14 DB11 GND DB17 GND QB13 QB11 D RXOA QA0 QA2 FLA DB8 DB10 DB7 VCC QB12 QB10 QB8 WXOA/ E QA1 QA4 QA3 PAEA DB9 DB6 VCC VCC QB9 QB7 HFA F QA5 QA6 GND VCC GND GND GND VCC GND QB6 QB5 WXOB/ G QA7 QA9 VCC VCC DA6 DA9 PAEB QB3 QB4 QB1 HFB H QA8 QA10 QA12 VCC DA7 DA10 DA8 FLB QB2 QB0 RXOB WXIB RXIB FFB J QA11 QA13 GND DA17 GND DA11 DA14 DB5 K QA14 QA15 EFA OEA RENA DA15 DA12 DB2 WENB DB4 PAFB L QA16 QA17 RSA LDA RCKLA DA16 DA13 DB0 DB1 DB3 WCLKB 123 456 789 10 11 3139 drw 02 PBGA (BG121, order code: BG) TOP VIEW NOTE: 1. The PBGA is only available for the IDT72805LB/72815LB/72825LB in the 15 or 25 ns speed grade. 2