Product Information

82P5088BBG

82P5088BBG electronic component of Renesas

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Telecom Interface ICs T1/E1/J1 UNIVERSAL OCTAL TRANSCEIVER

Manufacturer: Renesas
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1: USD 75.222 ea
Line Total: USD 75.22

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
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0 - Global Stock


Ships to you between Thu. 09 May to Mon. 13 May

MOQ : 1
Multiples : 1

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82P5088BBG
Renesas

1 : USD 72.3289
10 : USD 65.9464
25 : USD 63.8181
90 : USD 62.213

     
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IDT82P5088 Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter FEATURES Eight channel T1/E1/J1 long haul/short haul line interfaces - Active level of transmit data (TDATA) and receive data (RDATA) Supports HPS (Hitless Protection Switching) for 1+1 protection - Receiver or transmitter power down without external relays - High impedance setting for line drivers Receiver sensitivity exceeds -36 dB 772KHz and -43 dB 1024 - PRBS (Pseudo Random Bit Sequence) generation and detection 15 KHz with 2 -1 PRBS polynomials for E1 Programmable T1/E1/J1 switchability allowing one bill of ma- - QRSS (Quasi Random Sequence Signals) generation and detection terial for any line condition 20 with 2 -1 QRSS polynomials for T1/J1 3.3 V and 1.8 V power supply with 5 V tolerant inputs - 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS Meets or exceeds specifications in error counter - ANSI T1.102, T1.403 and T1.408 - Analog loopback, Digital loopback, Remote loopback and Inband - ITU I.431, G.703,G.736, G.775 and G.823 loopback - ETSI 300-166, 300-233 and TBR 12/13 Per channel cable attenuation indication - AT&T Pub 62411 Adaptive receive sensitivity Per channel software selectable on: Non-intrusive monitoring per ITU G.772 specification - Wave-shaping templates for short haul and long haul LBO (Line Build Short circuit protection for line drivers Out) LOS (Loss Of Signal) & AIS (alarm indication signal) detection - Line terminating impedance (T1:100 , J1:110 E1:75 120 JTAG interface - Adjustment of arbitrary pulse shape Supports serial control interface, Motorola and Intel Non-Multi- - JA (jitter attenuator) position (receive path and transmit path) plexed interfaces - Single rail/dual rail system interfaces Package: - B8ZS/HDB3/AMI line encoding/decoding Available in 256-pin BGA - Active edge of transmit clock (TCLK) and receive clock (RCLK) Green package options available DESCRIPTION The IDT82P5088 is an eight port line intereface that can be configured maintenance, a PRBS/QRSS generation/detection circuit is integrated in per port to any combination of T1, E1 or J1 ports. In receive path, an adaptive each channel, and different types of loopbacks can be set on a per channel equalizer is integrated to remove the distortion introduced by the cable basis. Four different kinds of line terminating impedance, 75 , 100 110 attenuation. The IDT82P5088 also performs clock/data recovery, AMI/ and 120 are selectable on a per channel basis. The chip also provides B8ZS/HDB3 line decoding and detects and reports the LOS conditions. In driver short-circuit protection and supports JTAG boundary scanning. the transmit path, there is an AMI/B8ZS/HDB3 encoder, waveform shaper, The IDT82P5088 can be used in SDH/SONET, WAN, routers, wireless LBOs and jitter attenuator for each channel. The jitter attenuators in both base stations, IADs, IMA, IMAPs, gateways, frame relay access devices, the transmit path and receive path can be disabled. The IDT82P5088 sup- CSU/DSU equipment, etc. ports both single rail and dual rail system interfaces. To facilitate network IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 July 30, 2014 2014 Integrated Device Technology, Inc. VERSION 2 DSC-7216/-IDT82P5088 UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER FUNCTIONAL BLOCK DIAGRAM TDO TDI TMS TCK TRST GPIO 1:0 RESET THZ A 10:0 D 7:1 D 0 /SDO CS REFR RW/WR/SDI DS/RD/SCLK MPM SPIEN INT REFB OUT REFA OUT CLK SEL 2:0 OSCO OSCI CLK GEN 1.544 CLK GEN 2.048 Figure-1 Block Diagram FUNCTIONAL BLOCK DIAGRAM 2 July 30, 2014 One of the Eight Identical Channels LOS/AIS LOSn Detector Receiver RCLKn B8ZS/ Clock and RTIPn Jitter Data Adaptive RDn/RDPn Internal HDB3/AMI Data Attenuator Slicer Equalizer Termination RRINGn CVn/RDNn Decoder Recovery PRBS Detector Analog Remote Digital IBLC Detector Loopback Loopback Loopback B8ZS/ TTIPn TCLKn Transmitter Jitter Waveform Line TDn/TDPn HDB3/AMI Internal Attenuator Shaper/LBO Driver TDNn Encoder Termination TRINGn PRBS Generator IBLC Generator TAOS G.772 Control Interface JTAG TAP Clock Generator Monitor VDDDIO / VDDDC / VDDAR / VDDAT / VDDAX / VDDAP / VDDAB GNDD / GNDA

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
CEL (RENESAS)
ID4
IDT
IDT, Integrated Device Technology Inc
INTEGRATED DEVICE
INTEGRATED DEVICE TECHNOLOGY
INTEGRATED DEVICES TECH AID
Intersil
INTERSIL - FGC
Intersil(Renes as Electronics)
Intersil(Renesas Electronics)
ITS
REA
RENESAS
RENESAS (IDT)
RENESAS (INTERSIL)
Renesas / IDT
Renesas / Intersil
Renesas Electronics
Renesas Electronics America
RENESAS TECHNOLOGY

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